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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-01 08:27:43 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-01 08:27:43 +0200 |
| commit | 696ac56744d9ec0177ea75fb166baf622fb905dd (patch) | |
| tree | 97f8fa33c2486f796157acf1ff6b73b17570b902 | |
| parent | d973dea41f3d5c7f9484657ba252296847894c20 (diff) | |
| download | ghdl-696ac56744d9ec0177ea75fb166baf622fb905dd.tar.gz ghdl-696ac56744d9ec0177ea75fb166baf622fb905dd.tar.bz2 ghdl-696ac56744d9ec0177ea75fb166baf622fb905dd.zip | |
synth: handle file flush procedure
| -rw-r--r-- | src/synth/elab-vhdl_files.adb | 14 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_files.ads | 2 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_static_proc.adb | 2 |
3 files changed, 18 insertions, 0 deletions
diff --git a/src/synth/elab-vhdl_files.adb b/src/synth/elab-vhdl_files.adb index 12afedd91..c2a8dc35f 100644 --- a/src/synth/elab-vhdl_files.adb +++ b/src/synth/elab-vhdl_files.adb @@ -395,6 +395,20 @@ package body Elab.Vhdl_Files is end if; end Synth_File_Close; + procedure Synth_File_Flush + (Syn_Inst : Synth_Instance_Acc; Imp : Node; Loc : Node) + is + Inters : constant Node := Get_Interface_Declaration_Chain (Imp); + F : constant File_Index := Get_Value (Syn_Inst, Inters).Val.File; + Status : Op_Status; + begin + Ghdl_File_Flush (F, Status); + + if Status /= Op_Ok then + File_Error (Loc, Status); + end if; + end Synth_File_Flush; + -- Declaration: -- procedure untruncated_text_read --!V87 -- (file f : text; str : out string; len : out natural); --!V87 diff --git a/src/synth/elab-vhdl_files.ads b/src/synth/elab-vhdl_files.ads index 959add1b0..7d48f6b08 100644 --- a/src/synth/elab-vhdl_files.ads +++ b/src/synth/elab-vhdl_files.ads @@ -40,6 +40,8 @@ package Elab.Vhdl_Files is (Syn_Inst : Synth_Instance_Acc; Imp : Node); procedure Synth_File_Close (Syn_Inst : Synth_Instance_Acc; Imp : Node; Loc : Node); + procedure Synth_File_Flush + (Syn_Inst : Synth_Instance_Acc; Imp : Node; Loc : Node); procedure Synth_Untruncated_Text_Read (Syn_Inst : Synth_Instance_Acc; Imp : Node; Loc : Node); diff --git a/src/synth/synth-vhdl_static_proc.adb b/src/synth/synth-vhdl_static_proc.adb index 9a724cc89..9144d5061 100644 --- a/src/synth/synth-vhdl_static_proc.adb +++ b/src/synth/synth-vhdl_static_proc.adb @@ -94,6 +94,8 @@ package body Synth.Vhdl_Static_Proc is Synth_File_Read (Syn_Inst, Imp, Loc); when Iir_Predefined_Write => Synth_File_Write (Syn_Inst, Imp, Loc); + when Iir_Predefined_Flush => + Synth_File_Flush (Syn_Inst, Imp, Loc); when Iir_Predefined_Std_Env_Finish_Status => if Hook_Finish /= null then Hook_Finish.all (Syn_Inst, Imp); |