aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* vhdl-sem_decls: handle protected type subtypesTristan Gingold2022-09-251-1/+4
| | | | Fix #2196
* testsuite/gna: add a test for #2198Tristan Gingold2022-09-252-0/+60
|
* vhdl-sem_names: handle architecture bodies in sem_denoting_nameTristan Gingold2022-09-251-1/+2
| | | | Fix #2198
* synth-vhdl_stmts: fix missing newline in default assertion messagesTristan Gingold2022-09-251-3/+3
|
* synth: handle default expression for IN variables in assocsTristan Gingold2022-09-251-4/+10
|
* synth: handle selected names in targetsTristan Gingold2022-09-251-1/+2
|
* synth-vhdl_eval: handle null-null in array concatenationsTristan Gingold2022-09-251-0/+6
|
* simul: gather disconnection specifications, create guard signalTristan Gingold2022-09-254-36/+194
|
* synth: ignore groups and group templatesTristan Gingold2022-09-253-1/+15
|
* grt: do not initialial GUARD signals on creation.Tristan Gingold2022-09-251-1/+4
|
* synth: handle attribute namesTristan Gingold2022-09-251-13/+16
|
* synth: handle individual subprogram associations for expressionsTristan Gingold2022-09-251-55/+61
|
* simul: handle empty proceduresTristan Gingold2022-09-251-1/+9
|
* synth: rework association conversionsTristan Gingold2022-09-253-62/+75
|
* synth-vhdl_stmts: rework for subprogram associations (WIP)Tristan Gingold2022-09-251-57/+36
|
* synth-vhdl_stmts: support of individual paramater associations (WIP)Tristan Gingold2022-09-252-106/+238
|
* simul: reuse drivers extraction from elaborationTristan Gingold2022-09-252-74/+26
|
* synth-vhdl_stmts: refactore synth_subprogram_associationsTristan Gingold2022-09-251-49/+52
|
* suite_driver.sh: print a message in case of failureTristan Gingold2022-09-251-0/+1
|
* synth-vhdl_stmts: refactoreTristan Gingold2022-09-251-23/+32
|
* synth-vhdl_stmts: refactoringTristan Gingold2022-09-251-189/+208
|
* synth-vhdl_stmts: rework in progress of subprogram associationsTristan Gingold2022-09-251-108/+115
|
* pyGHDL: added missing type annotations. Fix #2192 (#2195)fhuemer2022-09-231-2/+2
|
* synth-vhdl_insts: move pragma unreferencedTristan Gingold2022-09-211-1/+2
|
* configure: tentatively enable llvm 15Tristan Gingold2022-09-211-0/+1
|
* synth: simplify elab-vhdl_annotationsTristan Gingold2022-09-192-51/+3
|
* synth: simplify elab-vhdl_annotationsTristan Gingold2022-09-195-197/+31
|
* synth: rename vhdl.annotations to elab.vhdl_annotationsTristan Gingold2022-09-198-18/+20
|
* synth: rework subprogram associations (WIP)Tristan Gingold2022-09-193-42/+87
|
* synth-vhdl_stmts: minor renamingTristan Gingold2022-09-184-12/+12
|
* synth: fix assert failure on attribute specificationTristan Gingold2022-09-181-1/+5
|
* simul: handle individual port associations with expressionsTristan Gingold2022-09-181-1/+5
|
* simul: handle type conversions in port associationsTristan Gingold2022-09-183-49/+57
|
* synth: handle open variable associationTristan Gingold2022-09-171-22/+31
|
* simul: fix resolved associationTristan Gingold2022-09-172-2/+3
|
* simul: use synth_declarations for processes and proceduresTristan Gingold2022-09-174-18/+15
|
* synth: factorize code (reuse synth_constant_declaration)Tristan Gingold2022-09-178-71/+22
|
* synth: handle protected types in subprogramsTristan Gingold2022-09-173-38/+53
|
* synth: improve file handling (skip extra data, errors)Tristan Gingold2022-09-173-3/+53
|
* synth: finalize filesTristan Gingold2022-09-173-4/+30
|
* synth: handle read length on text filesTristan Gingold2022-09-171-16/+40
|
* synth: handle incomplete typesTristan Gingold2022-09-176-24/+87
|
* synth: handle individual generic associationsTristan Gingold2022-09-171-5/+35
|
* synth: factorize code with synth_assignment_prefixTristan Gingold2022-09-161-75/+15
|
* synth: preliminary work to factorize codeTristan Gingold2022-09-166-52/+69
|
* simul: handle active attributeTristan Gingold2022-09-164-11/+58
|
* synth: handle val attribute for static bit/logic valuesTristan Gingold2022-09-161-0/+3
|
* simul: improve support of concurrent procedure callTristan Gingold2022-09-161-1/+20
|
* simul: improve error handling during elaborationTristan Gingold2022-09-162-5/+6
|
* synth: improve handling of complex typesTristan Gingold2022-09-154-8/+30
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 08:43:50 +0000