7 files changed, 35 insertions, 15 deletions

diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb
index ae768b3d0..fcac44e3d 100644
--- a/src/vhdl/simulate/simul-simulation-main.adb
+++ b/src/vhdl/simulate/simul-simulation-main.adb
@@ -374,7 +374,8 @@ package body Simul.Simulation.Main is
       use PSL.Nodes;
    begin
       case Get_Kind (Expr) is
-         when N_HDL_Expr =>
+         when N_HDL_Expr
+           | N_HDL_Bool =>
             declare
                E : constant Iir := Get_HDL_Node (Expr);
                Rtype : constant Iir := Get_Base_Type (Get_Type (E));
diff --git a/src/vhdl/translate/trans-chap9.adb b/src/vhdl/translate/trans-chap9.adb
index 5211451e3..c10c0d24f 100644
--- a/src/vhdl/translate/trans-chap9.adb
+++ b/src/vhdl/translate/trans-chap9.adb
@@ -376,7 +376,8 @@ package body Trans.Chap9 is
       use PSL.Nodes;
    begin
       case Get_Kind (Expr) is
-         when N_HDL_Expr =>
+         when N_HDL_Bool
+           | N_HDL_Expr =>
             declare
                E     : constant Iir := Get_HDL_Node (Expr);
                Rtype : constant Iir := Get_Base_Type (Get_Type (E));
diff --git a/src/vhdl/vhdl-canon.adb b/src/vhdl/vhdl-canon.adb
index 3cd7bf736..90ef9cac6 100644
--- a/src/vhdl/vhdl-canon.adb
+++ b/src/vhdl/vhdl-canon.adb
@@ -850,7 +850,8 @@ package body Vhdl.Canon is
       use PSL.Nodes;
    begin
       case Get_Kind (Expr) is
-         when N_HDL_Expr =>
+         when N_HDL_Expr
+           | N_HDL_Bool =>
             Canon_Expression (Get_HDL_Node (Expr));
          when N_True | N_EOS =>
             null;
diff --git a/src/vhdl/vhdl-canon_psl.adb b/src/vhdl/vhdl-canon_psl.adb
index a130b0a5e..e505b655c 100644
--- a/src/vhdl/vhdl-canon_psl.adb
+++ b/src/vhdl/vhdl-canon_psl.adb
@@ -28,7 +28,8 @@ package body Vhdl.Canon_PSL is
    is
    begin
       case Get_Kind (Expr) is
-         when N_HDL_Expr =>
+         when N_HDL_Expr
+           | N_HDL_Bool =>
             Canon_Extract_Sensitivity (Get_HDL_Node (Expr), Sensitivity_List);
          when N_And_Bool
            | N_Or_Bool =>
diff --git a/src/vhdl/vhdl-parse_psl.adb b/src/vhdl/vhdl-parse_psl.adb
index 4dffbe38a..b664ec5c2 100644
--- a/src/vhdl/vhdl-parse_psl.adb
+++ b/src/vhdl/vhdl-parse_psl.adb
@@ -734,6 +734,7 @@ package body Vhdl.Parse_Psl is
            | N_Paren_Bool
            | N_Fusion_SERE
            | N_HDL_Expr
+           | N_HDL_Bool
            | N_Hdl_Mod_Name
            | N_Concat_SERE
            | N_Within_SERE
diff --git a/src/vhdl/vhdl-prints.adb b/src/vhdl/vhdl-prints.adb
index 59f25a08d..22bfa05cd 100644
--- a/src/vhdl/vhdl-prints.adb
+++ b/src/vhdl/vhdl-prints.adb
@@ -1959,7 +1959,8 @@ package body Vhdl.Prints is
             end;
          when N_Name_Decl =>
             Disp_Ident (Ctxt, Get_Identifier (N));
-         when N_HDL_Expr =>
+         when N_HDL_Expr
+           | N_HDL_Bool =>
             Print (Ctxt, Vhdl_Node (PSL.Nodes.Get_HDL_Node (N)));
             --  FIXME: this is true only when using the scanner.
             --  Print_Expr (Node (Get_HDL_Node (N)));
diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb
index ca9192cb2..f82299f44 100644
--- a/src/vhdl/vhdl-sem_psl.adb
+++ b/src/vhdl/vhdl-sem_psl.adb
@@ -130,15 +130,24 @@ package body Vhdl.Sem_Psl is
             --  Get the named entity for names in order to hash it.
             declare
                Name : Iir;
+               Hnode : PSL_Node;
+               N : PSL_Node;
             begin
                Name := Get_Named_Entity (Expr);
                if Name /= Null_Iir then
-                  return PSL.Hash.Get_PSL_Node (HDL_Node (Name));
+                  Hnode := PSL.Hash.Get_PSL_Node (HDL_Node (Name));
+                  N := Create_Node (N_HDL_Expr);
+                  Set_Location (N, Get_Location (Expr));
+                  Set_HDL_Node (N, HDL_Node (Expr));
+                  Set_HDL_Hash (N, Hnode);
+                  return N;
                end if;
             end;
          when others =>
             null;
       end case;
+
+      --  Default.
       return PSL.Hash.Get_PSL_Node (HDL_Node (Expr));
    end Convert_Bool;
 
@@ -615,7 +624,8 @@ package body Vhdl.Sem_Psl is
       end Rewrite_Monadic_Operator;
    begin
       case Get_Kind (Prop) is
-         when N_HDL_Expr =>
+         when N_HDL_Expr
+           | N_HDL_Bool =>
             return Get_HDL_Node (Prop);
          when N_And_Bool =>
             return Rewrite_Dyadic_Operator (Prop, Iir_Kind_And_Operator);
@@ -631,13 +641,16 @@ package body Vhdl.Sem_Psl is
             begin
                Res := Create_Iir (Iir_Kind_Parenthesis_Expression);
                Set_Location (Res, Get_Location (Prop));
-               if Get_Kind (Expr) = N_HDL_Expr then
-                  Hexpr := Get_HDL_Node (Expr);
-                  Set_Expression (Res, Hexpr);
-                  Set_Type (Res, Get_Type (Hexpr));
-               else
-                  Set_Expression (Res, Rewrite_As_Boolean_Expression (Expr));
-               end if;
+               case Get_Kind (Expr) is
+                  when N_HDL_Expr
+                    | N_HDL_Bool =>
+                     Hexpr := Get_HDL_Node (Expr);
+                     Set_Expression (Res, Hexpr);
+                     Set_Type (Res, Get_Type (Hexpr));
+                  when others =>
+                     Hexpr := Rewrite_As_Boolean_Expression (Expr);
+                     Set_Expression (Res, Hexpr);
+               end case;
                return Res;
             end;
          when others =>
@@ -676,7 +689,8 @@ package body Vhdl.Sem_Psl is
    function Is_Boolean_Assertion (Expr : PSL_Node) return Boolean is
    begin
       case Get_Kind (Expr) is
-         when N_HDL_Expr =>
+         when N_HDL_Expr
+           | N_HDL_Bool =>
             return True;
          when N_And_Bool | N_Or_Bool | N_Not_Bool | N_Paren_Bool =>
             return True;