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-rw-r--r--src/vhdl/simulate/simul-simulation-main.adb3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb
index ae768b3d0..fcac44e3d 100644
--- a/src/vhdl/simulate/simul-simulation-main.adb
+++ b/src/vhdl/simulate/simul-simulation-main.adb
@@ -374,7 +374,8 @@ package body Simul.Simulation.Main is
use PSL.Nodes;
begin
case Get_Kind (Expr) is
- when N_HDL_Expr =>
+ when N_HDL_Expr
+ | N_HDL_Bool =>
declare
E : constant Iir := Get_HDL_Node (Expr);
Rtype : constant Iir := Get_Base_Type (Get_Type (E));