8 files changed, 10 insertions, 10 deletions
diff --git a/src/vhdl/simulate/simul-debugger.adb b/src/vhdl/simulate/simul-debugger.adb
index 93f926048..e656e0ff6 100644
--- a/src/vhdl/simulate/simul-debugger.adb
+++ b/src/vhdl/simulate/simul-debugger.adb
@@ -31,7 +31,7 @@ with Vhdl.Canon;
 with Std_Names;
 with Libraries;
 with Vhdl.Std_Package;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 with Simul.Elaboration; use Simul.Elaboration;
 with Simul.Execution; use Simul.Execution;
 with Vhdl.Utils; use Vhdl.Utils;
diff --git a/src/vhdl/simulate/simul-elaboration.ads b/src/vhdl/simulate/simul-elaboration.ads
index 4c26b7d28..63fd11157 100644
--- a/src/vhdl/simulate/simul-elaboration.ads
+++ b/src/vhdl/simulate/simul-elaboration.ads
@@ -19,7 +19,7 @@
 with Tables;
 with Types; use Types;
 with Vhdl.Nodes; use Vhdl.Nodes;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 with Simul.Environments; use Simul.Environments;
 with Grt.Types; use Grt.Types;
 
diff --git a/src/vhdl/simulate/simul-environments.ads b/src/vhdl/simulate/simul-environments.ads
index 30f49aae0..dd0ca8b55 100644
--- a/src/vhdl/simulate/simul-environments.ads
+++ b/src/vhdl/simulate/simul-environments.ads
@@ -18,7 +18,7 @@
 
 with Ada.Unchecked_Deallocation;
 with Vhdl.Nodes; use Vhdl.Nodes;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 with Grt.Types; use Grt.Types;
 with Grt.Signals; use Grt.Signals;
 with Grt.Files;
diff --git a/src/vhdl/simulate/simul-execution.ads b/src/vhdl/simulate/simul-execution.ads
index e121a1bc8..567c13132 100644
--- a/src/vhdl/simulate/simul-execution.ads
+++ b/src/vhdl/simulate/simul-execution.ads
@@ -17,7 +17,7 @@
 --  02111-1307, USA.
 
 with Vhdl.Nodes; use Vhdl.Nodes;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 with Simul.Environments; use Simul.Environments;
 with Simul.Elaboration; use Simul.Elaboration;
 with Areapools; use Areapools;
diff --git a/src/vhdl/simulate/simul-file_operation.adb b/src/vhdl/simulate/simul-file_operation.adb
index 98b1729c2..0b687ef1e 100644
--- a/src/vhdl/simulate/simul-file_operation.adb
+++ b/src/vhdl/simulate/simul-file_operation.adb
@@ -17,7 +17,7 @@
 --  02111-1307, USA.
 
 with Types; use Types;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 with Simul.Execution; use Simul.Execution;
 with Simul.Debugger; use Simul.Debugger;
 with Simul.Grt_Interface; use Simul.Grt_Interface;
diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb
index 25250706a..461aeaad0 100644
--- a/src/vhdl/simulate/simul-simulation-main.adb
+++ b/src/vhdl/simulate/simul-simulation-main.adb
@@ -30,7 +30,7 @@ with Vhdl.Std_Package;
 with Trans_Analyzes;
 with Simul.Elaboration; use Simul.Elaboration;
 with Simul.Execution; use Simul.Execution;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 with Vhdl.Ieee.Std_Logic_1164;
 with Grt.Main;
 with Simul.Debugger; use Simul.Debugger;
diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/vhdl-annotations.adb
index 18b41561c..ace106d4f 100644
--- a/src/vhdl/simulate/simul-annotations.adb
+++ b/src/vhdl/vhdl-annotations.adb
@@ -23,7 +23,7 @@ with Vhdl.Errors; use Vhdl.Errors;
 with Vhdl.Utils; use Vhdl.Utils;
 with Vhdl.Ieee.Std_Logic_1164;
 
-package body Simul.Annotations is
+package body Vhdl.Annotations is
    procedure Annotate_Declaration_List
      (Block_Info: Sim_Info_Acc; Decl_Chain: Iir);
    procedure Annotate_Sequential_Statement_Chain
@@ -1312,4 +1312,4 @@ package body Simul.Annotations is
    begin
       return Info_Node.Table (Target);
    end Get_Info;
-end Simul.Annotations;
+end Vhdl.Annotations;
diff --git a/src/vhdl/simulate/simul-annotations.ads b/src/vhdl/vhdl-annotations.ads
index 52d637907..5da4ed175 100644
--- a/src/vhdl/simulate/simul-annotations.ads
+++ b/src/vhdl/vhdl-annotations.ads
@@ -19,7 +19,7 @@
 with Types; use Types;
 with Vhdl.Nodes; use Vhdl.Nodes;
 
-package Simul.Annotations is
+package Vhdl.Annotations is
    --  If True, annotate for synthesis.
    Flag_Synthesis : Boolean := False;
 
@@ -155,4 +155,4 @@ package Simul.Annotations is
    --  Expand the annotation table.  This is automatically done by Annotate,
    --  to be used only by debugger.
    procedure Annotate_Expand_Table;
-end Simul.Annotations;
+end Vhdl.Annotations;