16 files changed, 23 insertions, 23 deletions
diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb
index 52408b067..97adef30d 100644
--- a/src/ghdldrv/ghdlsimul.adb
+++ b/src/ghdldrv/ghdlsimul.adb
@@ -27,7 +27,7 @@ with Flags;
 with Vhdl.Std_Package;
 with Vhdl.Canon;
 with Vhdl.Configuration;
-with Simul.Annotations;
+with Vhdl.Annotations;
 with Simul.Elaboration;
 with Simul.Simulation.Main;
 with Simul.Debugger;
@@ -67,9 +67,9 @@ package body Ghdlsimul is
       Common_Compile_Elab (Cmd_Name, Args, Opt_Arg, Top_Conf);
 
       --  Annotate all units.
-      Simul.Annotations.Annotate (Vhdl.Std_Package.Std_Standard_Unit);
+      Vhdl.Annotations.Annotate (Vhdl.Std_Package.Std_Standard_Unit);
       for I in Design_Units.First .. Design_Units.Last loop
-         Simul.Annotations.Annotate (Design_Units.Table (I));
+         Vhdl.Annotations.Annotate (Design_Units.Table (I));
       end loop;
    end Compile_Elab;
 
diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb
index d02386eea..70315dc31 100644
--- a/src/ghdldrv/ghdlsynth.adb
+++ b/src/ghdldrv/ghdlsynth.adb
@@ -27,7 +27,7 @@ with Vhdl.Nodes; use Vhdl.Nodes;
 with Vhdl.Std_Package;
 with Vhdl.Canon;
 with Vhdl.Configuration;
-with Simul.Annotations;
+with Vhdl.Annotations;
 
 with Synthesis;
 with Netlists.Dump;
@@ -92,7 +92,7 @@ package body Ghdlsynth is
          end if;
       end loop;
 
-      Simul.Annotations.Flag_Synthesis := True;
+      Vhdl.Annotations.Flag_Synthesis := True;
 
       Common_Compile_Init (False);
       Flags.Flag_Elaborate_With_Outdated := False;
@@ -117,9 +117,9 @@ package body Ghdlsynth is
       end if;
 
       --  Annotate all units.
-      Simul.Annotations.Annotate (Vhdl.Std_Package.Std_Standard_Unit);
+      Vhdl.Annotations.Annotate (Vhdl.Std_Package.Std_Standard_Unit);
       for I in Design_Units.First .. Design_Units.Last loop
-         Simul.Annotations.Annotate (Design_Units.Table (I));
+         Vhdl.Annotations.Annotate (Design_Units.Table (I));
       end loop;
 
       return Synthesis.Synth_Design (Config);
diff --git a/src/synth/synth-context.ads b/src/synth/synth-context.ads
index e09702e1d..bb633b17c 100644
--- a/src/synth/synth-context.ads
+++ b/src/synth/synth-context.ads
@@ -20,7 +20,7 @@
 
 with Synth.Environment; use Synth.Environment;
 with Synth.Values; use Synth.Values;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 with Netlists; use Netlists;
 with Netlists.Builders;
 with Vhdl.Nodes; use Vhdl.Nodes;
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb
index b9ce77fed..0726cfa6d 100644
--- a/src/synth/synth-decls.adb
+++ b/src/synth/synth-decls.adb
@@ -28,7 +28,7 @@ with Synth.Types; use Synth.Types;
 with Synth.Values; use Synth.Values;
 with Synth.Environment; use Synth.Environment;
 with Synth.Expr; use Synth.Expr;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 
 package body Synth.Decls is
    procedure Synth_Anonymous_Subtype_Indication
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index 3f6e2efc5..4b48ae83a 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -29,7 +29,7 @@ with Vhdl.Utils; use Vhdl.Utils;
 with Vhdl.Evaluation; use Vhdl.Evaluation;
 
 with Areapools;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 
 with Synth.Errors; use Synth.Errors;
 with Synth.Types; use Synth.Types;
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb
index b43170078..0f374a904 100644
--- a/src/synth/synth-stmts.adb
+++ b/src/synth/synth-stmts.adb
@@ -37,7 +37,7 @@ with Synth.Expr; use Synth.Expr;
 with Synth.Values; use Synth.Values;
 with Synth.Environment; use Synth.Environment;
 
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 
 with Netlists; use Netlists;
 with Netlists.Builders; use Netlists.Builders;
diff --git a/src/synth/synth-types.adb b/src/synth/synth-types.adb
index ff516bac0..87034036e 100644
--- a/src/synth/synth-types.adb
+++ b/src/synth/synth-types.adb
@@ -26,7 +26,7 @@ with Vhdl.Errors; use Vhdl.Errors;
 
 with Synth.Values; use Synth.Values;
 with Synth.Expr;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 
 package body Synth.Types is
    function Is_Bit_Type (Atype : Iir) return Boolean is
diff --git a/src/synth/synthesis.adb b/src/synth/synthesis.adb
index b17cff003..a9ce60085 100644
--- a/src/synth/synthesis.adb
+++ b/src/synth/synthesis.adb
@@ -25,7 +25,7 @@ with Netlists.Builders; use Netlists.Builders;
 with Netlists.Utils;
 
 with Vhdl.Utils; use Vhdl.Utils;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 
 with Synth.Environment; use Synth.Environment;
 with Synth.Values; use Synth.Values;
diff --git a/src/vhdl/simulate/simul-debugger.adb b/src/vhdl/simulate/simul-debugger.adb
index 93f926048..e656e0ff6 100644
--- a/src/vhdl/simulate/simul-debugger.adb
+++ b/src/vhdl/simulate/simul-debugger.adb
@@ -31,7 +31,7 @@ with Vhdl.Canon;
 with Std_Names;
 with Libraries;
 with Vhdl.Std_Package;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 with Simul.Elaboration; use Simul.Elaboration;
 with Simul.Execution; use Simul.Execution;
 with Vhdl.Utils; use Vhdl.Utils;
diff --git a/src/vhdl/simulate/simul-elaboration.ads b/src/vhdl/simulate/simul-elaboration.ads
index 4c26b7d28..63fd11157 100644
--- a/src/vhdl/simulate/simul-elaboration.ads
+++ b/src/vhdl/simulate/simul-elaboration.ads
@@ -19,7 +19,7 @@
 with Tables;
 with Types; use Types;
 with Vhdl.Nodes; use Vhdl.Nodes;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 with Simul.Environments; use Simul.Environments;
 with Grt.Types; use Grt.Types;
 
diff --git a/src/vhdl/simulate/simul-environments.ads b/src/vhdl/simulate/simul-environments.ads
index 30f49aae0..dd0ca8b55 100644
--- a/src/vhdl/simulate/simul-environments.ads
+++ b/src/vhdl/simulate/simul-environments.ads
@@ -18,7 +18,7 @@
 
 with Ada.Unchecked_Deallocation;
 with Vhdl.Nodes; use Vhdl.Nodes;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 with Grt.Types; use Grt.Types;
 with Grt.Signals; use Grt.Signals;
 with Grt.Files;
diff --git a/src/vhdl/simulate/simul-execution.ads b/src/vhdl/simulate/simul-execution.ads
index e121a1bc8..567c13132 100644
--- a/src/vhdl/simulate/simul-execution.ads
+++ b/src/vhdl/simulate/simul-execution.ads
@@ -17,7 +17,7 @@
 --  02111-1307, USA.
 
 with Vhdl.Nodes; use Vhdl.Nodes;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 with Simul.Environments; use Simul.Environments;
 with Simul.Elaboration; use Simul.Elaboration;
 with Areapools; use Areapools;
diff --git a/src/vhdl/simulate/simul-file_operation.adb b/src/vhdl/simulate/simul-file_operation.adb
index 98b1729c2..0b687ef1e 100644
--- a/src/vhdl/simulate/simul-file_operation.adb
+++ b/src/vhdl/simulate/simul-file_operation.adb
@@ -17,7 +17,7 @@
 --  02111-1307, USA.
 
 with Types; use Types;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 with Simul.Execution; use Simul.Execution;
 with Simul.Debugger; use Simul.Debugger;
 with Simul.Grt_Interface; use Simul.Grt_Interface;
diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb
index 25250706a..461aeaad0 100644
--- a/src/vhdl/simulate/simul-simulation-main.adb
+++ b/src/vhdl/simulate/simul-simulation-main.adb
@@ -30,7 +30,7 @@ with Vhdl.Std_Package;
 with Trans_Analyzes;
 with Simul.Elaboration; use Simul.Elaboration;
 with Simul.Execution; use Simul.Execution;
-with Simul.Annotations; use Simul.Annotations;
+with Vhdl.Annotations; use Vhdl.Annotations;
 with Vhdl.Ieee.Std_Logic_1164;
 with Grt.Main;
 with Simul.Debugger; use Simul.Debugger;
diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/vhdl-annotations.adb
index 18b41561c..ace106d4f 100644
--- a/src/vhdl/simulate/simul-annotations.adb
+++ b/src/vhdl/vhdl-annotations.adb
@@ -23,7 +23,7 @@ with Vhdl.Errors; use Vhdl.Errors;
 with Vhdl.Utils; use Vhdl.Utils;
 with Vhdl.Ieee.Std_Logic_1164;
 
-package body Simul.Annotations is
+package body Vhdl.Annotations is
    procedure Annotate_Declaration_List
      (Block_Info: Sim_Info_Acc; Decl_Chain: Iir);
    procedure Annotate_Sequential_Statement_Chain
@@ -1312,4 +1312,4 @@ package body Simul.Annotations is
    begin
       return Info_Node.Table (Target);
    end Get_Info;
-end Simul.Annotations;
+end Vhdl.Annotations;
diff --git a/src/vhdl/simulate/simul-annotations.ads b/src/vhdl/vhdl-annotations.ads
index 52d637907..5da4ed175 100644
--- a/src/vhdl/simulate/simul-annotations.ads
+++ b/src/vhdl/vhdl-annotations.ads
@@ -19,7 +19,7 @@
 with Types; use Types;
 with Vhdl.Nodes; use Vhdl.Nodes;
 
-package Simul.Annotations is
+package Vhdl.Annotations is
    --  If True, annotate for synthesis.
    Flag_Synthesis : Boolean := False;
 
@@ -155,4 +155,4 @@ package Simul.Annotations is
    --  Expand the annotation table.  This is automatically done by Annotate,
    --  to be used only by debugger.
    procedure Annotate_Expand_Table;
-end Simul.Annotations;
+end Vhdl.Annotations;