testsuite/synth: add a test for #1428

23 files changed, 257 insertions, 0 deletions

diff --git a/testsuite/synth/issue1428/rec1.ref b/testsuite/synth/issue1428/rec1.ref
new file mode 100644
index 000000000..0fc9ff612
--- /dev/null
+++ b/testsuite/synth/issue1428/rec1.ref
@@ -0,0 +1,3 @@
+rec1.vhdl:15:10: multiple assignments for "s" offsets 1:1
+rec1.vhdl:15:10:note:  this concerns these parts of the signal:
+rec1.vhdl:15:10:note:   s.b
diff --git a/testsuite/synth/issue1428/rec1.vhdl b/testsuite/synth/issue1428/rec1.vhdl
new file mode 100644
index 000000000..db81be87d
--- /dev/null
+++ b/testsuite/synth/issue1428/rec1.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity rec1 is
+  port (a : out std_logic;
+        b : std_logic_vector(7 downto 0));
+end;
+
+architecture behav of rec1 is
+  type my_rec is record
+    a : std_logic;
+    b : std_logic;
+  end record;
+
+  signal s : my_rec;
+begin
+  s.b <= s.a;
+  a <= s.b;
+
+  s.a <= '1' when b /= x"00" else '0';
+
+  s.b <= '0';
+end behav;
diff --git a/testsuite/synth/issue1428/rec2.ref b/testsuite/synth/issue1428/rec2.ref
new file mode 100644
index 000000000..3d4465ba1
--- /dev/null
+++ b/testsuite/synth/issue1428/rec2.ref
@@ -0,0 +1,3 @@
+rec2.vhdl:15:10: multiple assignments for "s" offsets 2:2
+rec2.vhdl:15:10:note:  this concerns these parts of the signal:
+rec2.vhdl:15:10:note:   s.b(1)
diff --git a/testsuite/synth/issue1428/rec2.vhdl b/testsuite/synth/issue1428/rec2.vhdl
new file mode 100644
index 000000000..7e76664d7
--- /dev/null
+++ b/testsuite/synth/issue1428/rec2.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity rec2 is
+  port (a : out std_logic;
+        b : std_logic_vector(7 downto 0));
+end;
+
+architecture behav of rec2 is
+  type my_rec is record
+    a : std_logic;
+    b : std_logic_vector(7 downto 0);
+  end record;
+
+  signal s : my_rec;
+begin
+  s.b <= b;
+  a <= s.a;
+
+  s.a <= '1' when s.b /= x"00" else '0';
+
+  s.b (1) <= '0';
+end behav;
diff --git a/testsuite/synth/issue1428/rec3.ref b/testsuite/synth/issue1428/rec3.ref
new file mode 100644
index 000000000..21a8d0b89
--- /dev/null
+++ b/testsuite/synth/issue1428/rec3.ref
@@ -0,0 +1,3 @@
+rec3.vhdl:16:10: multiple assignments for "s" offsets 1:1
+rec3.vhdl:16:10:note:  this concerns these parts of the signal:
+rec3.vhdl:16:10:note:   s.b
diff --git a/testsuite/synth/issue1428/rec3.vhdl b/testsuite/synth/issue1428/rec3.vhdl
new file mode 100644
index 000000000..4b7cf9ec5
--- /dev/null
+++ b/testsuite/synth/issue1428/rec3.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity rec3 is
+  port (a : out std_logic;
+        b : std_logic_vector(7 downto 0));
+end;
+
+architecture behav of rec3 is
+  type my_rec is record
+    a : std_logic;
+    b : std_logic;
+    c : std_logic;
+  end record;
+
+  signal s : my_rec;
+begin
+  s.a <= b (0);
+  s.b <= b (1);
+  s.c <= b (2);
+  a <= s.a;
+
+  s.b <= '0';
+end behav;
diff --git a/testsuite/synth/issue1428/repro1.ref b/testsuite/synth/issue1428/repro1.ref
new file mode 100644
index 000000000..b050c02a2
--- /dev/null
+++ b/testsuite/synth/issue1428/repro1.ref
@@ -0,0 +1,3 @@
+repro1.vhdl:15:10: multiple assignments for "s" offsets 2:2
+repro1.vhdl:15:10:note:  this concerns these parts of the signal:
+repro1.vhdl:15:10:note:   s.b(1)
diff --git a/testsuite/synth/issue1428/repro1.vhdl b/testsuite/synth/issue1428/repro1.vhdl
new file mode 100644
index 000000000..a4b8d8466
--- /dev/null
+++ b/testsuite/synth/issue1428/repro1.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro1 is
+  port (a : out std_logic;
+        b : std_logic_vector(7 downto 0));
+end;
+
+architecture behav of repro1 is
+  type my_rec is record
+    a : std_logic;
+    b : std_logic_vector(7 downto 0);
+  end record;
+
+  signal s : my_rec;
+begin
+  s.b <= b;
+  a <= s.a;
+
+  s.a <= '1' when s.b /= x"00" else '0';
+
+  s.b (1) <= '0';
+end behav;
diff --git a/testsuite/synth/issue1428/repro2.ref b/testsuite/synth/issue1428/repro2.ref
new file mode 100644
index 000000000..c2977ee57
--- /dev/null
+++ b/testsuite/synth/issue1428/repro2.ref
@@ -0,0 +1,3 @@
+repro2.vhdl:10:10: multiple assignments for "s" offsets 0:0
+repro2.vhdl:10:10:note:  this concerns these parts of the signal:
+repro2.vhdl:10:10:note:   s(0)
diff --git a/testsuite/synth/issue1428/repro2.vhdl b/testsuite/synth/issue1428/repro2.vhdl
new file mode 100644
index 000000000..21c15b1c9
--- /dev/null
+++ b/testsuite/synth/issue1428/repro2.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro2 is
+  port (a : out std_logic;
+        b : std_logic_vector(7 downto 0));
+end;
+
+architecture behav of repro2 is
+  signal s : std_logic_vector(7 downto 0);
+begin
+  s <= b;
+  a <= '1' when s /= x"00" else '0';
+
+  s (0) <= '0';
+end behav;
diff --git a/testsuite/synth/issue1428/repro3.ref b/testsuite/synth/issue1428/repro3.ref
new file mode 100644
index 000000000..b5d258321
--- /dev/null
+++ b/testsuite/synth/issue1428/repro3.ref
@@ -0,0 +1,3 @@
+repro3.vhdl:10:10: multiple assignments for "s" offsets 5:5
+repro3.vhdl:10:10:note:  this concerns these parts of the signal:
+repro3.vhdl:10:10:note:   s(5)
diff --git a/testsuite/synth/issue1428/repro3.vhdl b/testsuite/synth/issue1428/repro3.vhdl
new file mode 100644
index 000000000..4a9c092c5
--- /dev/null
+++ b/testsuite/synth/issue1428/repro3.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro3 is
+  port (a : out std_logic;
+        b : std_logic_vector(7 downto 0));
+end;
+
+architecture behav of repro3 is
+  signal s : std_logic_vector(7 downto 0);
+begin
+  s <= b;
+  a <= '1' when s /= x"00" else '0';
+
+  s (5) <= '0';
+end behav;
diff --git a/testsuite/synth/issue1428/repro4.ref b/testsuite/synth/issue1428/repro4.ref
new file mode 100644
index 000000000..c6f74a9c8
--- /dev/null
+++ b/testsuite/synth/issue1428/repro4.ref
@@ -0,0 +1,6 @@
+repro4.vhdl:10:10: multiple assignments for "s" offsets 3:3
+repro4.vhdl:10:10:note:  this concerns these parts of the signal:
+repro4.vhdl:10:10:note:   s(3)
+repro4.vhdl:10:10: multiple assignments for "s" offsets 5:5
+repro4.vhdl:10:10:note:  this concerns these parts of the signal:
+repro4.vhdl:10:10:note:   s(5)
diff --git a/testsuite/synth/issue1428/repro4.vhdl b/testsuite/synth/issue1428/repro4.vhdl
new file mode 100644
index 000000000..dce256fd4
--- /dev/null
+++ b/testsuite/synth/issue1428/repro4.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro4 is
+  port (a : out std_logic;
+        b : std_logic_vector(7 downto 0));
+end;
+
+architecture behav of repro4 is
+  signal s : std_logic_vector(7 downto 0);
+begin
+  s <= b;
+  a <= '1' when s /= x"00" else '0';
+
+  s (3) <= '0';
+  s (5) <= '0';
+end behav;
diff --git a/testsuite/synth/issue1428/repro4b.ref b/testsuite/synth/issue1428/repro4b.ref
new file mode 100644
index 000000000..a86824596
--- /dev/null
+++ b/testsuite/synth/issue1428/repro4b.ref
@@ -0,0 +1,6 @@
+repro4b.vhdl:10:10: multiple assignments for "s" offsets 3:3
+repro4b.vhdl:10:10:note:  this concerns these parts of the signal:
+repro4b.vhdl:10:10:note:   s(5)
+repro4b.vhdl:10:10: multiple assignments for "s" offsets 6:6
+repro4b.vhdl:10:10:note:  this concerns these parts of the signal:
+repro4b.vhdl:10:10:note:   s(2)
diff --git a/testsuite/synth/issue1428/repro4b.vhdl b/testsuite/synth/issue1428/repro4b.vhdl
new file mode 100644
index 000000000..1c94809fd
--- /dev/null
+++ b/testsuite/synth/issue1428/repro4b.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro4b is
+  port (a : out std_logic;
+        b : std_logic_vector(7 downto 0));
+end;
+
+architecture behav of repro4b is
+  signal s : std_logic_vector(1 to 8);
+begin
+  s <= b;
+  a <= '1' when s /= x"00" else '0';
+
+  s (2) <= '0';
+  s (5) <= '0';
+end behav;
diff --git a/testsuite/synth/issue1428/repro5.ref b/testsuite/synth/issue1428/repro5.ref
new file mode 100644
index 000000000..dfee31b3e
--- /dev/null
+++ b/testsuite/synth/issue1428/repro5.ref
@@ -0,0 +1,3 @@
+repro5.vhdl:10:10: multiple assignments for "s" offsets 4:5
+repro5.vhdl:10:10:note:  this concerns these parts of the signal:
+repro5.vhdl:10:10:note:   s(5 downto 4)
diff --git a/testsuite/synth/issue1428/repro5.vhdl b/testsuite/synth/issue1428/repro5.vhdl
new file mode 100644
index 000000000..4363e6103
--- /dev/null
+++ b/testsuite/synth/issue1428/repro5.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro5 is
+  port (a : out std_logic;
+        b : std_logic_vector(7 downto 0));
+end;
+
+architecture behav of repro5 is
+  signal s : std_logic_vector(7 downto 0);
+begin
+  s <= b;
+  a <= '1' when s /= x"00" else '0';
+
+  s (5 downto 4) <= "00";
+end behav;
diff --git a/testsuite/synth/issue1428/repro5b.ref b/testsuite/synth/issue1428/repro5b.ref
new file mode 100644
index 000000000..adcabfb14
--- /dev/null
+++ b/testsuite/synth/issue1428/repro5b.ref
@@ -0,0 +1,3 @@
+repro5b.vhdl:10:10: multiple assignments for "s" offsets 4:6
+repro5b.vhdl:10:10:note:  this concerns these parts of the signal:
+repro5b.vhdl:10:10:note:   s(2 to 4)
diff --git a/testsuite/synth/issue1428/repro5b.vhdl b/testsuite/synth/issue1428/repro5b.vhdl
new file mode 100644
index 000000000..299b3ccc4
--- /dev/null
+++ b/testsuite/synth/issue1428/repro5b.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro5b is
+  port (a : out std_logic;
+        b : std_logic_vector(7 downto 0));
+end;
+
+architecture behav of repro5b is
+  signal s : std_logic_vector(1 to 8);
+begin
+  s <= b;
+  a <= '1' when s /= x"00" else '0';
+
+  s (2 to 4) <= "000";
+end behav;
diff --git a/testsuite/synth/issue1428/repro6.ref b/testsuite/synth/issue1428/repro6.ref
new file mode 100644
index 000000000..2a774445b
--- /dev/null
+++ b/testsuite/synth/issue1428/repro6.ref
@@ -0,0 +1,3 @@
+repro6.vhdl:10:10: multiple assignments for "s" offsets 4:5
+repro6.vhdl:10:10:note:  this concerns these parts of the signal:
+repro6.vhdl:10:10:note:   s(5 downto 4)
diff --git a/testsuite/synth/issue1428/repro6.vhdl b/testsuite/synth/issue1428/repro6.vhdl
new file mode 100644
index 000000000..977ddab0e
--- /dev/null
+++ b/testsuite/synth/issue1428/repro6.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro6 is
+  port (a : out std_logic;
+        b : std_logic_vector(7 downto 0));
+end;
+
+architecture behav of repro6 is
+  signal s : std_logic_vector(7 downto 0);
+begin
+  s (5 downto 0) <= b (5 downto 0);
+  a <= '1' when s /= x"00" else '0';
+
+  s (7 downto 4) <= "0000";
+end behav;
diff --git a/testsuite/synth/issue1428/testsuite.sh b/testsuite/synth/issue1428/testsuite.sh
new file mode 100755
index 000000000..d7d647dd1
--- /dev/null
+++ b/testsuite/synth/issue1428/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in rec1 rec2 rec3 repro1 repro2 repro3 repro4b repro4 repro5b repro5 repro6
+do
+    synth --expect-failure $t.vhdl -e 2>&1 | grep $t.vhdl: > $t.out
+    diff --strip-trailing-cr $t.out $t.ref
+done
+
+echo "Test successful"