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-rw-r--r--testsuite/synth/issue1428/repro5.vhdl16
1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/synth/issue1428/repro5.vhdl b/testsuite/synth/issue1428/repro5.vhdl
new file mode 100644
index 000000000..4363e6103
--- /dev/null
+++ b/testsuite/synth/issue1428/repro5.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro5 is
+ port (a : out std_logic;
+ b : std_logic_vector(7 downto 0));
+end;
+
+architecture behav of repro5 is
+ signal s : std_logic_vector(7 downto 0);
+begin
+ s <= b;
+ a <= '1' when s /= x"00" else '0';
+
+ s (5 downto 4) <= "00";
+end behav;