testsuite/synth: add a test for #1896

3 files changed, 44 insertions, 1 deletions

diff --git a/testsuite/synth/oper02/tb_uns02.vhdl b/testsuite/synth/oper02/tb_uns02.vhdl
new file mode 100644
index 000000000..025d56e81
--- /dev/null
+++ b/testsuite/synth/oper02/tb_uns02.vhdl
@@ -0,0 +1,20 @@
+entity tb_uns02 is
+end tb_uns02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_uns02 is
+  signal r : boolean;
+begin
+  cmp01_1: entity work.uns02
+    port map (r);
+
+  process
+  begin
+    wait for 1 ns;
+    assert r severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/oper02/testsuite.sh b/testsuite/synth/oper02/testsuite.sh
index c240d1184..6fb2d7ca4 100755
--- a/testsuite/synth/oper02/testsuite.sh
+++ b/testsuite/synth/oper02/testsuite.sh
@@ -3,7 +3,7 @@
 . ../../testenv.sh
 
 GHDL_STD_FLAGS=--std=08
-for t in min01 max01; do
+for t in min01 max01 uns02; do
     synth_tb $t
 done
 
diff --git a/testsuite/synth/oper02/uns02.vhdl b/testsuite/synth/oper02/uns02.vhdl
new file mode 100644
index 000000000..e03ffc6f7
--- /dev/null
+++ b/testsuite/synth/oper02/uns02.vhdl
@@ -0,0 +1,23 @@
+entity uns02 is
+  port (ok : out boolean);
+end uns02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of uns02 is
+  --  add uns uns
+  constant a : unsigned (7 downto 0) := x"1e";
+  constant b : unsigned (3 downto 0) := x"2";
+  constant r1 : unsigned (7 downto 0) := a - b;
+  signal er1 : unsigned (7 downto 0);
+  signal ok1 : boolean;
+  constant cok1 : boolean := and(a) = '0';
+  constant cok2 : boolean := or(a) = '1';
+begin
+  assert cok1 and cok2 severity failure;
+  er1 <= x"1c";
+  ok1 <= and(er1) = '0';
+  ok <= ok1;
+end behav;