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author | Tristan Gingold <tgingold@free.fr> | 2021-06-21 07:43:55 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-06-21 08:07:13 +0200 |
commit | 09e1764ea6dcf08aa77f8b6f5115caca9de44057 (patch) | |
tree | c66014ebe875cad6ed20c6b7de326dab30b16286 /testsuite/synth | |
parent | 6aaabbfc1716fffd7b7185d53e791e77400950d2 (diff) | |
download | ghdl-09e1764ea6dcf08aa77f8b6f5115caca9de44057.tar.gz ghdl-09e1764ea6dcf08aa77f8b6f5115caca9de44057.tar.bz2 ghdl-09e1764ea6dcf08aa77f8b6f5115caca9de44057.zip |
testsuite/synth: check ram in mem01 and mem02
Diffstat (limited to 'testsuite/synth')
-rwxr-xr-x | testsuite/synth/mem01/testsuite.sh | 10 | ||||
-rw-r--r-- | testsuite/synth/mem02/ram3.vhdl | 2 | ||||
-rw-r--r-- | testsuite/synth/mem02/ram4.vhdl | 1 | ||||
-rw-r--r-- | testsuite/synth/mem02/ram6.vhdl | 2 | ||||
-rwxr-xr-x | testsuite/synth/mem02/testsuite.sh | 15 | ||||
-rw-r--r-- | testsuite/synth/mem2d01/dpram1r.vhdl | 1 | ||||
-rw-r--r-- | testsuite/synth/mem2d01/dpram2r.vhdl | 1 | ||||
-rw-r--r-- | testsuite/synth/mem2d01/dpram2w.vhdl | 1 | ||||
-rwxr-xr-x | testsuite/synth/mem2d01/testsuite.sh | 14 | ||||
-rwxr-xr-x | testsuite/synth/synth109/testsuite.sh | 15 |
10 files changed, 34 insertions, 28 deletions
diff --git a/testsuite/synth/mem01/testsuite.sh b/testsuite/synth/mem01/testsuite.sh index 186456831..00e9022a9 100755 --- a/testsuite/synth/mem01/testsuite.sh +++ b/testsuite/synth/mem01/testsuite.sh @@ -3,14 +3,10 @@ . ../../testenv.sh for t in rom1 srom01 sram01 sram02 sram03 sram05 dpram1 dpram2 dpram3; do - analyze $t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean + synth_tb $t 2> $t.log - synth $t.vhdl -e $t > syn_$t.vhdl - analyze syn_$t.vhdl tb_$t.vhdl - elab_simulate tb_$t --ieee-asserts=disable-at-0 - clean + # Each design has either a RAM or a ROM + grep 'found R' $t.log done echo "Test successful" diff --git a/testsuite/synth/mem02/ram3.vhdl b/testsuite/synth/mem02/ram3.vhdl index d67667c3e..3988be036 100644 --- a/testsuite/synth/mem02/ram3.vhdl +++ b/testsuite/synth/mem02/ram3.vhdl @@ -21,5 +21,7 @@ begin mem(ra) <= wdat; end if; end process; + + -- As MEM is read in a whole, this is not a RAM. val <= mem; end behav; diff --git a/testsuite/synth/mem02/ram4.vhdl b/testsuite/synth/mem02/ram4.vhdl index c397e44f1..c96208f7b 100644 --- a/testsuite/synth/mem02/ram4.vhdl +++ b/testsuite/synth/mem02/ram4.vhdl @@ -22,6 +22,7 @@ begin begin if rising_edge (clk) then if rst = '1' then + -- As MEM is written in a whole, this is not a RAM. mem <= init; end if; rdat <= mem((idx.idx+1) * 2 - 1 downto idx.idx * 2); diff --git a/testsuite/synth/mem02/ram6.vhdl b/testsuite/synth/mem02/ram6.vhdl index 621e7cc27..70eb21054 100644 --- a/testsuite/synth/mem02/ram6.vhdl +++ b/testsuite/synth/mem02/ram6.vhdl @@ -21,5 +21,7 @@ begin mem(ra) <= wdat; end if; end process; + + -- As MEM is read in a whole, this is not a RAM val <= mem; end behav; diff --git a/testsuite/synth/mem02/testsuite.sh b/testsuite/synth/mem02/testsuite.sh index fd8a749c3..1250b3f39 100755 --- a/testsuite/synth/mem02/testsuite.sh +++ b/testsuite/synth/mem02/testsuite.sh @@ -2,15 +2,14 @@ . ../../testenv.sh -for t in dpram1 ram3 ram4 ram6; do - analyze $t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean +for t in dpram1; do + synth_tb $t 2> $t.log + grep "found R" $t.log +done - synth $t.vhdl -e $t > syn_$t.vhdl - analyze syn_$t.vhdl tb_$t.vhdl - elab_simulate tb_$t --ieee-asserts=disable-at-0 - clean +# Designs that doesn't create a RAM/ROM +for t in ram3 ram4 ram6; do + synth_tb $t 2> $t.log done synth ram8.vhdl -e > syn_ram8.vhdl diff --git a/testsuite/synth/mem2d01/dpram1r.vhdl b/testsuite/synth/mem2d01/dpram1r.vhdl index 2c1335a1b..30c0f9f39 100644 --- a/testsuite/synth/mem2d01/dpram1r.vhdl +++ b/testsuite/synth/mem2d01/dpram1r.vhdl @@ -18,6 +18,7 @@ begin process (clk) begin if rising_edge (clk) then + -- Not a memory: uses different widths. rdat <= mem (raddr)(rbit); mem (waddr) <= wdat; end if; diff --git a/testsuite/synth/mem2d01/dpram2r.vhdl b/testsuite/synth/mem2d01/dpram2r.vhdl index 4419d5086..0b3c4646a 100644 --- a/testsuite/synth/mem2d01/dpram2r.vhdl +++ b/testsuite/synth/mem2d01/dpram2r.vhdl @@ -18,6 +18,7 @@ begin process (clk) begin if rising_edge (clk) then + -- Not a memory: different widths rdat <= mem (raddr)(rnib * 4 + 3 downto rnib * 4); mem (waddr) <= wdat; end if; diff --git a/testsuite/synth/mem2d01/dpram2w.vhdl b/testsuite/synth/mem2d01/dpram2w.vhdl index c1b1c83d0..2c412824f 100644 --- a/testsuite/synth/mem2d01/dpram2w.vhdl +++ b/testsuite/synth/mem2d01/dpram2w.vhdl @@ -18,6 +18,7 @@ begin process (clk) begin if rising_edge (clk) then + -- Not a memory: different widths mem (waddr)(wnib * 4 + 3 downto wnib * 4) <= wdat; rdat <= mem (raddr); end if; diff --git a/testsuite/synth/mem2d01/testsuite.sh b/testsuite/synth/mem2d01/testsuite.sh index e885729f1..1c7c45546 100755 --- a/testsuite/synth/mem2d01/testsuite.sh +++ b/testsuite/synth/mem2d01/testsuite.sh @@ -2,15 +2,13 @@ . ../../testenv.sh -for t in dpram1r dpram2r dpram2w memmux04; do - analyze $t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean +for t in memmux04; do + synth_tb $t 2> $t.log + grep "found R" $t.log +done - synth $t.vhdl -e $t > syn_$t.vhdl - analyze syn_$t.vhdl tb_$t.vhdl - elab_simulate tb_$t --ieee-asserts=disable-at-0 - clean +for t in dpram1r dpram2r dpram2w; do + synth_tb $t 2> $t.log done echo "Test successful" diff --git a/testsuite/synth/synth109/testsuite.sh b/testsuite/synth/synth109/testsuite.sh index 11cb2e052..cc1803015 100755 --- a/testsuite/synth/synth109/testsuite.sh +++ b/testsuite/synth/synth109/testsuite.sh @@ -3,11 +3,16 @@ . ../../testenv.sh GHDL_STD_FLAGS="-fsynopsys" -synth_tb ram1 -synth_tb ram2 -synth_tb ram4 -synth_analyze ram9 -synth asymmetric_ram_2a.vhd -e > syn_asymmetric_ram_2a.vhdl +for t in ram1 ram2 ram4; do + synth_tb $t 2> $t.log + grep "found R" $t.log +done + +synth_analyze ram9 2> ram9.log +grep "found RAM" ram9.log + +synth asymmetric_ram_2a.vhd -e > syn_asymmetric_ram_2a.vhdl 2> ram_2a.log +grep "found RAM" ram_2a.log echo "Test successful" |