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authorTristan Gingold <tgingold@free.fr>2022-07-11 07:34:14 +0200
committerTristan Gingold <tgingold@free.fr>2022-07-11 07:34:14 +0200
commit02588566f171f87109d026f8fbbc39796eada17c (patch)
treedaed7f0c6ebcceb12becb24e1d9cd75d153a9213 /testsuite/synth
parent328aa863c6258c89e74ad04895dfc0484fe859e0 (diff)
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testsuite/synth: add a test for #2125
Diffstat (limited to 'testsuite/synth')
-rw-r--r--testsuite/synth/issue2125/a2.vhdl22
-rw-r--r--testsuite/synth/issue2125/a3.vhdl21
-rw-r--r--testsuite/synth/issue2125/afed.vhdl26
-rw-r--r--testsuite/synth/issue2125/afed_syn.vhdl30
-rw-r--r--testsuite/synth/issue2125/tb_afed.vhdl37
-rwxr-xr-xtestsuite/synth/issue2125/testsuite.sh16
6 files changed, 152 insertions, 0 deletions
diff --git a/testsuite/synth/issue2125/a2.vhdl b/testsuite/synth/issue2125/a2.vhdl
new file mode 100644
index 000000000..646d39fa4
--- /dev/null
+++ b/testsuite/synth/issue2125/a2.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity a2 is
+ port (
+ sig : in std_logic;
+ ack : in std_logic;
+ fe : out std_logic
+ );
+end entity;
+
+architecture behaviour of a2 is
+
+ signal fe_h : std_logic;
+
+begin
+
+ fe_h <= '0' when ack = '1' else
+ '1' when sig = '1';
+ fe <= fe_h;
+
+end architecture;
diff --git a/testsuite/synth/issue2125/a3.vhdl b/testsuite/synth/issue2125/a3.vhdl
new file mode 100644
index 000000000..0be5e440a
--- /dev/null
+++ b/testsuite/synth/issue2125/a3.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity a3 is
+ port (
+ sig : in std_logic;
+ ack : in std_logic;
+ fe : out std_logic
+ );
+end entity;
+
+architecture behaviour of a3 is
+
+ signal fe_h : std_logic;
+
+begin
+ fe <= fe_h;
+
+ fe_h <= '0' when ack = '1' else
+ '1' when sig = '1' else fe_h;
+end architecture;
diff --git a/testsuite/synth/issue2125/afed.vhdl b/testsuite/synth/issue2125/afed.vhdl
new file mode 100644
index 000000000..341545eb8
--- /dev/null
+++ b/testsuite/synth/issue2125/afed.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity afed is
+ port (
+ sig : in std_logic;
+ ack : in std_logic;
+ fe : out std_logic
+ );
+end entity;
+
+architecture behaviour of afed is
+
+ signal fe_h : std_logic;
+ signal fe_l : std_logic;
+
+begin
+
+ fe_h <= '0' when ack = '1' else
+ '1' when sig = '1';
+ fe_l <= '0' when ack = '1' else
+ '1' when sig = '0' and fe_h = '1';
+
+ fe <= fe_l;
+
+end architecture;
diff --git a/testsuite/synth/issue2125/afed_syn.vhdl b/testsuite/synth/issue2125/afed_syn.vhdl
new file mode 100644
index 000000000..7abf79752
--- /dev/null
+++ b/testsuite/synth/issue2125/afed_syn.vhdl
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity afed is
+ port (
+ sig: in std_logic;
+ ack: in std_logic;
+ fe: out std_logic
+ );
+end entity;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture rtl of afed is
+ signal fe_h : std_logic;
+ signal fe_l : std_logic;
+ signal n4_o : std_logic;
+ signal n9_o : std_logic;
+ signal n10_o : std_logic;
+begin
+ fe <= fe_l;
+
+ n4_o <= fe_h when sig = '0' else '1';
+ fe_h <= n4_o when ack = '0' else '0';
+
+ n9_o <= (not sig) and fe_h; -- 0
+ n10_o <= fe_l when n9_o = '0' else '1';
+ fe_l <= n10_o when ack = '0' else '0';
+end rtl;
diff --git a/testsuite/synth/issue2125/tb_afed.vhdl b/testsuite/synth/issue2125/tb_afed.vhdl
new file mode 100644
index 000000000..f120d2a58
--- /dev/null
+++ b/testsuite/synth/issue2125/tb_afed.vhdl
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_afed is
+end entity;
+
+architecture behaviour of tb_afed is
+
+ signal sig : std_logic := '1';
+ signal ack : std_logic := '1';
+ signal fe : std_logic;
+begin
+
+ monitor : process (fe)
+ begin
+ report std_logic'image(fe);
+ end process;
+
+ simu : process
+ begin
+ wait for 1 ns;
+ ack <= '0'; wait for 1 ns;
+ sig <= '1'; wait for 1 ns;
+ sig <= '0'; wait for 1 ns;
+ sig <= '1'; wait for 1 ns;
+ ack <= '1'; wait for 1 ns;
+ wait;
+ end process;
+
+ afed : entity work.afed
+ port map (
+ sig => sig,
+ ack => ack,
+ fe => fe
+ );
+
+end architecture;
diff --git a/testsuite/synth/issue2125/testsuite.sh b/testsuite/synth/issue2125/testsuite.sh
new file mode 100755
index 000000000..27230d8ff
--- /dev/null
+++ b/testsuite/synth/issue2125/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+# TODO: reuse synth_tb, but we need to pass --latches
+
+analyze afed.vhdl tb_afed.vhdl
+elab_simulate tb_afed
+clean
+
+synth --latches afed.vhdl -e > syn_afed.vhdl
+analyze syn_afed.vhdl tb_afed.vhdl
+elab_simulate tb_afed --ieee-asserts=disable-at-0 --assert-level=error
+clean
+
+echo "Test successful"