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author | Tristan Gingold <tgingold@free.fr> | 2022-01-18 07:50:14 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-02-05 17:06:03 +0100 |
commit | c953b83b8e7957125b14036f9368a6a7acf7f130 (patch) | |
tree | 8a6faf8be4e7375eb2e64319ffbee003fa43a098 /testsuite/synth/issue1951/sub02.vhdl | |
parent | 45d1b9308910d85bd391e2aabf882f1069dce649 (diff) | |
download | ghdl-c953b83b8e7957125b14036f9368a6a7acf7f130.tar.gz ghdl-c953b83b8e7957125b14036f9368a6a7acf7f130.tar.bz2 ghdl-c953b83b8e7957125b14036f9368a6a7acf7f130.zip |
testsuite/synth: add more tests for subtraction in std_logic_unsigned
Diffstat (limited to 'testsuite/synth/issue1951/sub02.vhdl')
-rw-r--r-- | testsuite/synth/issue1951/sub02.vhdl | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/testsuite/synth/issue1951/sub02.vhdl b/testsuite/synth/issue1951/sub02.vhdl new file mode 100644 index 000000000..ebe9be1f9 --- /dev/null +++ b/testsuite/synth/issue1951/sub02.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity sub02 is + port (i : std_logic_vector (3 downto 0); + o : out std_logic_vector (3 downto 0)); +end entity; + +architecture arch of sub02 is +begin + o <= i - (-7); +end arch; |