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author | Tristan Gingold <tgingold@free.fr> | 2019-05-19 18:53:40 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-05-19 20:34:12 +0200 |
commit | 9a183c7b6af43d741c77e419f33ed8e5d48001d1 (patch) | |
tree | b84f02d3486fa584a308dbd7ce31333fb4128d8f /testsuite/synth/dff01/dff06.vhdl | |
parent | bf6e695a130c85a6c17b543329831dd09ae40457 (diff) | |
download | ghdl-9a183c7b6af43d741c77e419f33ed8e5d48001d1.tar.gz ghdl-9a183c7b6af43d741c77e419f33ed8e5d48001d1.tar.bz2 ghdl-9a183c7b6af43d741c77e419f33ed8e5d48001d1.zip |
dff01: add more tests.
Diffstat (limited to 'testsuite/synth/dff01/dff06.vhdl')
-rw-r--r-- | testsuite/synth/dff01/dff06.vhdl | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/synth/dff01/dff06.vhdl b/testsuite/synth/dff01/dff06.vhdl new file mode 100644 index 000000000..33f5590a6 --- /dev/null +++ b/testsuite/synth/dff01/dff06.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff06 is + port (q : out std_logic; + d : std_logic; + clk : std_logic); +end dff06; + +architecture behav of dff06 is +begin + process (clk) is + variable a, b : std_logic; + begin + if rising_edge (clk) then + q <= b; + b := a; + a := d; + end if; + end process; +end behav; |