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authorTristan Gingold <tgingold@free.fr>2019-04-16 19:03:15 +0200
committerTristan Gingold <tgingold@free.fr>2019-04-16 19:03:15 +0200
commit5336f2f3fb7f43ec208f1357588195fc2d915637 (patch)
tree6acf49a00abac08d651817167841c96981c84653 /testsuite/synth/dff01/dff02.vhdl
parentbbbf1969105775e658d8d91c99b30f3934cb7275 (diff)
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testsuite: add dff01 tests.
Diffstat (limited to 'testsuite/synth/dff01/dff02.vhdl')
-rw-r--r--testsuite/synth/dff01/dff02.vhdl21
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/synth/dff01/dff02.vhdl b/testsuite/synth/dff01/dff02.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff02 is
+ port (q : out std_logic;
+ d : std_logic;
+ clk : std_logic;
+ rstn : std_logic);
+end dff02;
+
+architecture behav of dff02 is
+begin
+ process (clk, rstn) is
+ begin
+ if rstn = '0' then
+ q <= '0';
+ elsif rising_edge (clk) then
+ q <= d;
+ end if;
+ end process;
+end behav;