testsuite: add dff01 tests.

5 files changed, 90 insertions, 0 deletions

diff --git a/testsuite/synth/dff01/dff01.vhdl b/testsuite/synth/dff01/dff01.vhdl
new file mode 100644
index 000000000..feb9fac3f
--- /dev/null
+++ b/testsuite/synth/dff01/dff01.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff01 is
+  port (q : out std_logic;
+        d : std_logic;
+        clk : std_logic);
+end dff01;
+
+architecture behav of dff01 is
+begin
+  process (clk) is
+  begin
+    if rising_edge (clk) then
+      q <= d;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/dff02.vhdl b/testsuite/synth/dff01/dff02.vhdl
new file mode 100644
index 000000000..0d8eaf67d
--- /dev/null
+++ b/testsuite/synth/dff01/dff02.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff02 is
+  port (q : out std_logic;
+        d : std_logic;
+        clk : std_logic;
+        rstn : std_logic);
+end dff02;
+
+architecture behav of dff02 is
+begin
+  process (clk, rstn) is
+  begin
+    if rstn = '0' then
+      q <= '0';
+    elsif rising_edge (clk) then
+      q <= d;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/dff03.vhdl b/testsuite/synth/dff01/dff03.vhdl
new file mode 100644
index 000000000..718d5cacd
--- /dev/null
+++ b/testsuite/synth/dff01/dff03.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff03 is
+  port (q : out std_logic_vector(7 downto 0);
+        d : std_logic_vector(7 downto 0);
+        clk : std_logic);
+end dff03;
+
+architecture behav of dff03 is
+begin
+  process (clk) is
+  begin
+    if rising_edge (clk) then
+      q <= d;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/dff04.vhdl b/testsuite/synth/dff01/dff04.vhdl
new file mode 100644
index 000000000..9e7e60478
--- /dev/null
+++ b/testsuite/synth/dff01/dff04.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dff04 is
+  port (r : out std_logic_vector(7 downto 0);
+        d : std_logic_vector(7 downto 0);
+        clk : std_logic);
+end dff04;
+
+architecture behav of dff04 is
+  signal q : std_logic_vector(7 downto 0);
+begin
+  process (clk) is
+  begin
+    if rising_edge (clk) then
+      q <= d;
+    end if;
+    r <= std_logic_vector(unsigned(q) + 1);
+  end process;
+end behav;
diff --git a/testsuite/synth/dff01/testsuite.sh b/testsuite/synth/dff01/testsuite.sh
new file mode 100755
index 000000000..b8d3d335c
--- /dev/null
+++ b/testsuite/synth/dff01/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth dff01.vhdl -e dff01
+synth dff02.vhdl -e dff02
+synth dff03.vhdl -e dff03
+synth dff04.vhdl -e dff04
+
+clean
+
+echo "Test successful"