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authorTristan Gingold <tgingold@free.fr>2021-11-12 18:52:18 +0100
committerTristan Gingold <tgingold@free.fr>2021-11-12 18:52:58 +0100
commit56735b0d1e92b4246ef53442236e89afe07aacdc (patch)
tree7b0c825edbc6021b269e89d187bc06fb93e997ad /testsuite/synth/blackbox01/tb_blackbox1.vhdl
parentc2b6b4fe03c879753c76f5bee9f0ffe3b0e73f52 (diff)
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testsuite/synth: add a test for black boxes
Diffstat (limited to 'testsuite/synth/blackbox01/tb_blackbox1.vhdl')
-rw-r--r--testsuite/synth/blackbox01/tb_blackbox1.vhdl33
1 files changed, 33 insertions, 0 deletions
diff --git a/testsuite/synth/blackbox01/tb_blackbox1.vhdl b/testsuite/synth/blackbox01/tb_blackbox1.vhdl
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+entity tb_blackbox1 is
+end tb_blackbox1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_blackbox1 is
+ signal a, b : std_logic_vector(7 downto 0);
+ signal r :std_logic_vector(7 downto 0);
+begin
+ dut: entity work.blackbox1
+ port map (a, b, r);
+
+ process
+ begin
+ a <= x"40";
+ b <= x"04";
+ wait for 1 ns;
+ assert r = x"44" severity failure;
+
+ a <= x"b5";
+ b <= x"11";
+ wait for 1 ns;
+ assert r = x"c6" severity failure;
+
+ a <= x"b5";
+ b <= x"23";
+ wait for 1 ns;
+ assert r = x"c8" severity failure;
+
+ wait;
+ end process;
+end behav;