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authorTristan Gingold <tgingold@free.fr>2022-08-10 16:55:22 +0200
committerTristan Gingold <tgingold@free.fr>2022-08-10 16:55:22 +0200
commit4d14b77ce02b89b1a22718ce607b16d823d95c74 (patch)
tree6090f74b784e4768a6c1d7f8da9890f6da129f93 /testsuite/gna/issue2166/tb2.vhdl
parent8a3922778cd92df96aaf5771f24d650bb8290559 (diff)
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testsuite/gna: add a reproducer for #2166
Diffstat (limited to 'testsuite/gna/issue2166/tb2.vhdl')
-rw-r--r--testsuite/gna/issue2166/tb2.vhdl35
1 files changed, 35 insertions, 0 deletions
diff --git a/testsuite/gna/issue2166/tb2.vhdl b/testsuite/gna/issue2166/tb2.vhdl
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+++ b/testsuite/gna/issue2166/tb2.vhdl
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+library OSVVM ;
+
+use OSVVM.MemorySupportPkg.all ;
+
+package MemoryPkg is new OSVVM.MemoryGenericPkg
+ generic map (
+-- MemoryBaseType => MemoryBaseType_X,
+ SizeMemoryBaseType => SizeMemoryBaseType_X,
+ ToMemoryBaseType => ToMemoryBaseType_X,
+ FromMemoryBaseType => FromMemoryBaseType_X,
+ InitMemoryBaseType => InitMemoryBaseType_X
+ ) ;
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+use ieee.numeric_std.all ;
+use work.MemoryPkg.all;
+
+entity tb2 is
+end;
+
+architecture behav of tb2 is
+begin
+ process
+ variable MemoryID : MemoryIDType;
+ begin
+ MemoryID := NewID(
+ Name => "my_sram",
+ AddrWidth => 20,
+ DataWidth => 16);
+
+ MemWrite(MemoryId, x"00000", x"0000");
+ wait;
+ end process;
+end ;