testsuite/gna: add a test for #1474

Close #1474

3 files changed, 81 insertions, 0 deletions

diff --git a/testsuite/gna/issue1474/ent1.vhdl b/testsuite/gna/issue1474/ent1.vhdl
new file mode 100644
index 000000000..3e98b310e
--- /dev/null
+++ b/testsuite/gna/issue1474/ent1.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent1 is
+end entity;
+    
+architecture a of ent1 is
+    
+    type vector_array_t is array(natural range <>) of std_logic_vector;
+    
+    signal test : vector_array_t(7 downto 0)(7 downto 0);
+    signal test2 : std_logic_vector(63 downto 0);
+    
+    function concatenate(arr : vector_array_t) return std_logic_vector is
+		constant ARR_SIZE : natural := arr'length;
+		constant VEC_SIZE : natural := arr(arr'low)'length;
+		variable ret : std_logic_vector(ARR_SIZE * VEC_SIZE - 1 downto 0);
+	begin
+		for r in arr'range loop
+			ret((r+1) * VEC_SIZE - 1 downto r * VEC_SIZE) := arr(r);
+		end loop;
+		return ret;
+	end function;
+
+begin
+	test2 <= concatenate(test);
+end;
diff --git a/testsuite/gna/issue1474/ent2.vhdl b/testsuite/gna/issue1474/ent2.vhdl
new file mode 100644
index 000000000..e307a1cd9
--- /dev/null
+++ b/testsuite/gna/issue1474/ent2.vhdl
@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package pkg is
+
+	type vector_array_t is array(natural range <>) of std_logic_vector;
+	
+	function concatenate(arr : vector_array_t) return std_logic_vector;
+end package;
+
+package body pkg is
+
+    function concatenate(arr : vector_array_t) return std_logic_vector is
+		constant ARR_SIZE : natural := arr'length;
+		constant VEC_SIZE : natural := arr(arr'low)'length;
+		variable ret : std_logic_vector(ARR_SIZE * VEC_SIZE - 1 downto 0);
+	begin
+		for r in arr'range loop
+			ret((r+1) * VEC_SIZE - 1 downto r * VEC_SIZE) := arr(r);
+		end loop;
+		return ret;
+	end function;
+
+end package body;
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.pkg.all;
+
+entity ent2 is
+end entity;
+    
+architecture a of ent2 is
+	signal test : vector_array_t(7 downto 0)(7 downto 0);
+	signal test2 : std_logic_vector(63 downto 0);
+
+begin
+	test2 <= concatenate(test);
+end;
diff --git a/testsuite/gna/issue1474/testsuite.sh b/testsuite/gna/issue1474/testsuite.sh
new file mode 100755
index 000000000..2295d27ea
--- /dev/null
+++ b/testsuite/gna/issue1474/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze ent1.vhdl
+elab_simulate ent1
+
+analyze ent2.vhdl
+elab_simulate ent2
+
+clean
+
+echo "Test successful"