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Diffstat (limited to 'testsuite/gna/issue1474/ent1.vhdl')
-rw-r--r-- | testsuite/gna/issue1474/ent1.vhdl | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/gna/issue1474/ent1.vhdl b/testsuite/gna/issue1474/ent1.vhdl new file mode 100644 index 000000000..3e98b310e --- /dev/null +++ b/testsuite/gna/issue1474/ent1.vhdl @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent1 is +end entity; + +architecture a of ent1 is + + type vector_array_t is array(natural range <>) of std_logic_vector; + + signal test : vector_array_t(7 downto 0)(7 downto 0); + signal test2 : std_logic_vector(63 downto 0); + + function concatenate(arr : vector_array_t) return std_logic_vector is + constant ARR_SIZE : natural := arr'length; + constant VEC_SIZE : natural := arr(arr'low)'length; + variable ret : std_logic_vector(ARR_SIZE * VEC_SIZE - 1 downto 0); + begin + for r in arr'range loop + ret((r+1) * VEC_SIZE - 1 downto r * VEC_SIZE) := arr(r); + end loop; + return ret; + end function; + +begin + test2 <= concatenate(test); +end; |