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author | Tristan Gingold <tgingold@free.fr> | 2021-02-09 21:01:06 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-02-09 21:06:22 +0100 |
commit | d6b15882f1e023e3d68f424e76215c981ab0304b (patch) | |
tree | 6e6c0184e8d3e79dcd74b0416f79f939c7dcd8c1 /src/vhdl | |
parent | f195ad27e1810b1071d9fc72a1686d32597cf882 (diff) | |
download | ghdl-d6b15882f1e023e3d68f424e76215c981ab0304b.tar.gz ghdl-d6b15882f1e023e3d68f424e76215c981ab0304b.tar.bz2 ghdl-d6b15882f1e023e3d68f424e76215c981ab0304b.zip |
vhdl-sem_psl: factorize code for onehot/onehot0 and stable/fell/rose.
Diffstat (limited to 'src/vhdl')
-rw-r--r-- | src/vhdl/vhdl-sem_expr.adb | 18 | ||||
-rw-r--r-- | src/vhdl/vhdl-sem_psl.adb | 95 | ||||
-rw-r--r-- | src/vhdl/vhdl-sem_psl.ads | 9 |
3 files changed, 17 insertions, 105 deletions
diff --git a/src/vhdl/vhdl-sem_expr.adb b/src/vhdl/vhdl-sem_expr.adb index 25dbb1fea..c55377f46 100644 --- a/src/vhdl/vhdl-sem_expr.adb +++ b/src/vhdl/vhdl-sem_expr.adb @@ -4913,21 +4913,15 @@ package body Vhdl.Sem_Expr is when Iir_Kind_Psl_Prev => return Sem_Psl.Sem_Prev_Builtin (Expr, A_Type); - when Iir_Kind_Psl_Stable => - return Sem_Psl.Sem_Stable_Builtin (Expr); + when Iir_Kind_Psl_Stable + | Iir_Kind_Psl_Rose + | Iir_Kind_Psl_Fell => + return Sem_Psl.Sem_Clock_Builtin (Expr); - when Iir_Kind_Psl_Rose => - return Sem_Psl.Sem_Rose_Builtin (Expr); - - when Iir_Kind_Psl_Fell => - return Sem_Psl.Sem_Fell_Builtin (Expr); - - when Iir_Kind_Psl_Onehot => + when Iir_Kind_Psl_Onehot + | Iir_Kind_Psl_Onehot0 => return Sem_Psl.Sem_Onehot_Builtin (Expr); - when Iir_Kind_Psl_Onehot0 => - return Sem_Psl.Sem_Onehot0_Builtin (Expr); - when Iir_Kind_Error => -- Always ok. -- Use the error as a type. diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb index f8652f803..c73681b7c 100644 --- a/src/vhdl/vhdl-sem_psl.adb +++ b/src/vhdl/vhdl-sem_psl.adb @@ -121,7 +121,7 @@ package body Vhdl.Sem_Psl is return Call; end Sem_Prev_Builtin; - function Sem_Stable_Builtin (Call : Iir) return Iir + function Sem_Clock_Builtin (Call : Iir) return Iir is use Vhdl.Sem_Expr; use Vhdl.Std_Package; @@ -146,7 +146,7 @@ package body Vhdl.Sem_Psl is Set_Clock_Expression (Call, Clock); else if Current_Psl_Default_Clock = Null_Iir then - Error_Msg_Sem (+Call, "no clock for PSL stable builtin"); + Error_Msg_Sem (+Call, "no clock for %n", +Call); else Set_Default_Clock (Call, Current_Psl_Default_Clock); end if; @@ -154,77 +154,7 @@ package body Vhdl.Sem_Psl is end if; return Call; - end Sem_Stable_Builtin; - - function Sem_Rose_Builtin (Call : Iir) return Iir - is - use Vhdl.Sem_Expr; - use Vhdl.Std_Package; - Expr : Iir; - Clock : Iir; - First : Boolean; - begin - Expr := Get_Expression (Call); - First := Is_Expr_Not_Analyzed (Expr); - Expr := Sem_Expression (Expr, Null_Iir); - if Expr /= Null_Iir then - Set_Expression (Call, Expr); - Set_Type (Call, Vhdl.Std_Package.Boolean_Type_Definition); - Set_Expr_Staticness (Call, None); - end if; - - if First then - -- Analyze clock only once. - Clock := Get_Clock_Expression (Call); - if Clock /= Null_Iir then - Clock := Sem_Expression_Wildcard (Clock, Wildcard_Psl_Bit_Type); - Set_Clock_Expression (Call, Clock); - else - if Current_Psl_Default_Clock = Null_Iir then - Error_Msg_Sem (+Call, "no clock for PSL rose builtin"); - else - Set_Default_Clock (Call, Current_Psl_Default_Clock); - end if; - end if; - end if; - - return Call; - end Sem_Rose_Builtin; - - function Sem_Fell_Builtin (Call : Iir) return Iir - is - use Vhdl.Sem_Expr; - use Vhdl.Std_Package; - Expr : Iir; - Clock : Iir; - First : Boolean; - begin - Expr := Get_Expression (Call); - First := Is_Expr_Not_Analyzed (Expr); - Expr := Sem_Expression (Expr, Null_Iir); - if Expr /= Null_Iir then - Set_Expression (Call, Expr); - Set_Type (Call, Vhdl.Std_Package.Boolean_Type_Definition); - Set_Expr_Staticness (Call, None); - end if; - - if First then - -- Analyze clock only once. - Clock := Get_Clock_Expression (Call); - if Clock /= Null_Iir then - Clock := Sem_Expression_Wildcard (Clock, Wildcard_Psl_Bit_Type); - Set_Clock_Expression (Call, Clock); - else - if Current_Psl_Default_Clock = Null_Iir then - Error_Msg_Sem (+Call, "no clock for PSL fell builtin"); - else - Set_Default_Clock (Call, Current_Psl_Default_Clock); - end if; - end if; - end if; - - return Call; - end Sem_Fell_Builtin; + end Sem_Clock_Builtin; function Sem_Onehot_Builtin (Call : Iir) return Iir is @@ -238,26 +168,13 @@ package body Vhdl.Sem_Psl is Set_Expression (Call, Expr); Set_Type (Call, Vhdl.Std_Package.Boolean_Type_Definition); Set_Expr_Staticness (Call, None); + if not Is_Psl_Bitvector_Type (Get_Type (Expr)) then + Error_Msg_Sem (+Call, "type of parameter must be bitvector"); + end if; end if; return Call; end Sem_Onehot_Builtin; - function Sem_Onehot0_Builtin (Call : Iir) return Iir - is - use Vhdl.Sem_Expr; - use Vhdl.Std_Package; - Expr : Iir; - begin - Expr := Get_Expression (Call); - Expr := Sem_Expression (Expr, Null_Iir); - if Expr /= Null_Iir then - Set_Expression (Call, Expr); - Set_Type (Call, Vhdl.Std_Package.Boolean_Type_Definition); - Set_Expr_Staticness (Call, None); - end if; - return Call; - end Sem_Onehot0_Builtin; - -- Convert VHDL and/or/not nodes to PSL nodes. function Convert_Bool (Expr : Iir) return PSL_Node; diff --git a/src/vhdl/vhdl-sem_psl.ads b/src/vhdl/vhdl-sem_psl.ads index 758462a62..7cbb4bd8b 100644 --- a/src/vhdl/vhdl-sem_psl.ads +++ b/src/vhdl/vhdl-sem_psl.ads @@ -22,11 +22,12 @@ package Vhdl.Sem_Psl is function Is_Psl_Bitvector_Type (Atype : Iir) return Boolean; function Sem_Prev_Builtin (Call : Iir; Atype : Iir) return Iir; - function Sem_Stable_Builtin (Call : Iir) return Iir; - function Sem_Rose_Builtin (Call : Iir) return Iir; - function Sem_Fell_Builtin (Call : Iir) return Iir; + + -- For stable, rose and fell builtins. + function Sem_Clock_Builtin (Call : Iir) return Iir; + + -- For onehot and onehot0. function Sem_Onehot_Builtin (Call : Iir) return Iir; - function Sem_Onehot0_Builtin (Call : Iir) return Iir; procedure Sem_Psl_Declaration (Stmt : Iir); procedure Sem_Psl_Endpoint_Declaration (Stmt : Iir); |