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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-02 19:02:56 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-02 19:02:56 +0200 |
| commit | a11d847187413ad04a6d98c1e867ccb5e385abe5 (patch) | |
| tree | d451775064efe18c5510528e1efef86dad56224e /src/vhdl | |
| parent | c851b365a40b7643346beece274b1ba81d9af5e5 (diff) | |
| download | ghdl-a11d847187413ad04a6d98c1e867ccb5e385abe5.tar.gz ghdl-a11d847187413ad04a6d98c1e867ccb5e385abe5.tar.bz2 ghdl-a11d847187413ad04a6d98c1e867ccb5e385abe5.zip | |
synth: handle concurrent assertions.
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/vhdl-annotations.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index ace106d4f..2d02029ce 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -1051,7 +1051,8 @@ package body Vhdl.Annotations is when Iir_Kind_Concurrent_Simple_Signal_Assignment | Iir_Kind_Concurrent_Selected_Signal_Assignment - | Iir_Kind_Concurrent_Conditional_Signal_Assignment => + | Iir_Kind_Concurrent_Conditional_Signal_Assignment + | Iir_Kind_Concurrent_Assertion_Statement => -- In case concurrent signal assignemnts were not -- canonicalized (for synthesis). null; |