diff options
| -rw-r--r-- | src/synth/ghdlsynth_gates.h | 1 | ||||
| -rw-r--r-- | src/synth/netlists-builders.adb | 21 | ||||
| -rw-r--r-- | src/synth/netlists-builders.ads | 3 | ||||
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 2 | ||||
| -rw-r--r-- | src/synth/netlists-gates.ads | 3 | ||||
| -rw-r--r-- | src/synth/synth-stmts.adb | 18 | ||||
| -rw-r--r-- | src/vhdl/vhdl-annotations.adb | 3 |
7 files changed, 50 insertions, 1 deletions
diff --git a/src/synth/ghdlsynth_gates.h b/src/synth/ghdlsynth_gates.h index f80c53cc2..90872d312 100644 --- a/src/synth/ghdlsynth_gates.h +++ b/src/synth/ghdlsynth_gates.h @@ -53,6 +53,7 @@ enum Module_Id { Id_Insert = 48, Id_Dyn_Insert = 49, Id_Edge = 50, + Id_Assert = 51, Id_Const_UB32 = 56, Id_Const_SB32 = 57, Id_Const_UB64 = 58, diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb index f52ac4f56..d0106b10b 100644 --- a/src/synth/netlists-builders.adb +++ b/src/synth/netlists-builders.adb @@ -333,6 +333,17 @@ package body Netlists.Builders is Outputs); end Create_Dff_Modules; + procedure Create_Assert (Ctxt : Context_Acc) + is + Outputs : Port_Desc_Array (1 .. 0); + begin + Ctxt.M_Assert := New_User_Module + (Ctxt.Design, New_Sname_Artificial (Name_Assert), Id_Assert, + 1, 0, 0); + Set_Port_Desc (Ctxt.M_Assert, (0 => Create_Input ("cond", 1)), + Outputs); + end Create_Assert; + function Build_Builders (Design : Module) return Context_Acc is Res : Context_Acc; @@ -403,6 +414,8 @@ package body Netlists.Builders is Create_Objects_Module (Res); Create_Dff_Modules (Res); + Create_Assert (Res); + return Res; end Build_Builders; @@ -843,4 +856,12 @@ package body Netlists.Builders is return Build_Extract (Ctxt, I, Off, 1); end Build_Extract_Bit; + procedure Build_Assert (Ctxt : Context_Acc; Cond : Net) + is + Inst : Instance; + begin + Inst := New_Internal_Instance (Ctxt, Ctxt.M_Assert); + Connect (Get_Input (Inst, 0), Cond); + end Build_Assert; + end Netlists.Builders; diff --git a/src/synth/netlists-builders.ads b/src/synth/netlists-builders.ads index 214484168..9f7567ecb 100644 --- a/src/synth/netlists-builders.ads +++ b/src/synth/netlists-builders.ads @@ -89,6 +89,8 @@ package Netlists.Builders is function Build_Isignal (Ctxt : Context_Acc; Name : Sname; Init : Net) return Net; + procedure Build_Assert (Ctxt : Context_Acc; Cond : Net); + -- A simple flip-flop. function Build_Dff (Ctxt : Context_Acc; Clk : Net; @@ -134,5 +136,6 @@ private M_Insert : Module; M_Dyn_Extract : Module; M_Dyn_Insert : Module; + M_Assert : Module; end record; end Netlists.Builders; diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index bf53b4d1d..644ae0ce1 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -605,6 +605,8 @@ package body Netlists.Disp_Vhdl is Put ((1 .. Natural (Ow - Iw) => '0')); Disp_Template (""" & \i0; -- uext" & NL, Inst); end; + when Id_Assert => + Disp_Template (" assert \i0 = '1' severity error;" & NL, Inst); when others => Disp_Instance_Gate (Inst); end case; diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index 120088760..b150f158d 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -135,6 +135,9 @@ package Netlists.Gates is -- the detector. Id_Edge : constant Module_Id := 50; + -- Input signal must always be true. + Id_Assert : constant Module_Id := 51; + -- Constants are gates with only one constant output. There are multiple -- kind of constant gates: for small width, the value is stored as a -- parameter, possibly signed or unsigned extended. For large width diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 33d198d9f..3521fd2aa 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -1051,6 +1051,22 @@ package body Synth.Stmts is Instance_Pool := null; end Synth_Generate_Statement_Body; + procedure Synth_Concurrent_Assertion_Statement + (Syn_Inst : Synth_Instance_Acc; Stmt : Node) + is + Cond : constant Node := Get_Assertion_Condition (Stmt); + Val : Value_Acc; + begin + Val := Synth_Expression (Syn_Inst, Cond); + if Is_Const (Val) then + if Val.Scal /= 1 then + raise Internal_Error; + end if; + return; + end if; + Build_Assert (Build_Context, Get_Net (Val, Get_Type (Cond))); + end Synth_Concurrent_Assertion_Statement; + procedure Synth_Concurrent_Statements (Syn_Inst : Synth_Instance_Acc; Stmts : Node) is @@ -1085,6 +1101,8 @@ package body Synth.Stmts is exit when Gen = Null_Node; end loop; end; + when Iir_Kind_Concurrent_Assertion_Statement => + Synth_Concurrent_Assertion_Statement (Syn_Inst, Stmt); when Iir_Kind_Component_Instantiation_Statement => -- TODO. null; diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index ace106d4f..2d02029ce 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -1051,7 +1051,8 @@ package body Vhdl.Annotations is when Iir_Kind_Concurrent_Simple_Signal_Assignment | Iir_Kind_Concurrent_Selected_Signal_Assignment - | Iir_Kind_Concurrent_Conditional_Signal_Assignment => + | Iir_Kind_Concurrent_Conditional_Signal_Assignment + | Iir_Kind_Concurrent_Assertion_Statement => -- In case concurrent signal assignemnts were not -- canonicalized (for synthesis). null; |