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author | Tristan Gingold <tgingold@free.fr> | 2017-11-08 06:34:52 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-11-08 06:34:52 +0100 |
commit | 9a90393e30827308ec6cd834963f5359158115a0 (patch) | |
tree | ad9d89a3cf877a3870608b12989e6940b611fab1 /src/vhdl | |
parent | 4035edd1239f927ebd50fad88f01786db4d6a262 (diff) | |
download | ghdl-9a90393e30827308ec6cd834963f5359158115a0.tar.gz ghdl-9a90393e30827308ec6cd834963f5359158115a0.tar.bz2 ghdl-9a90393e30827308ec6cd834963f5359158115a0.zip |
Update simulate.
Diffstat (limited to 'src/vhdl')
-rw-r--r-- | src/vhdl/simulate/annotations.adb | 25 | ||||
-rw-r--r-- | src/vhdl/simulate/debugger.adb | 4 | ||||
-rw-r--r-- | src/vhdl/simulate/elaboration.adb | 46 | ||||
-rw-r--r-- | src/vhdl/simulate/execution.adb | 58 | ||||
-rw-r--r-- | src/vhdl/simulate/iir_values.adb | 6 | ||||
-rw-r--r-- | src/vhdl/simulate/simulation-main.adb | 5 | ||||
-rw-r--r-- | src/vhdl/simulate/simulation.adb | 2 |
7 files changed, 67 insertions, 79 deletions
diff --git a/src/vhdl/simulate/annotations.adb b/src/vhdl/simulate/annotations.adb index 34a2a88b9..484b9911d 100644 --- a/src/vhdl/simulate/annotations.adb +++ b/src/vhdl/simulate/annotations.adb @@ -167,15 +167,14 @@ package body Annotations is when Iir_Kind_Record_Type_Definition | Iir_Kind_Record_Subtype_Definition => declare + List : constant Iir_Flist := + Get_Elements_Declaration_List (Get_Base_Type (Def)); El : Iir; Res : Natural; - List : Iir_List; begin Res := 2; - List := Get_Elements_Declaration_List (Get_Base_Type (Def)); - for I in Natural loop + for I in Flist_First .. Flist_Last (List) loop El := Get_Nth_Element (List, I); - exit when El = Null_Iir; Res := Res + Get_File_Signature_Length (Get_Type (El)); end loop; return Res; @@ -206,15 +205,14 @@ package body Annotations is when Iir_Kind_Record_Type_Definition | Iir_Kind_Record_Subtype_Definition => declare + List : constant Iir_Flist := + Get_Elements_Declaration_List (Get_Base_Type (Def)); El : Iir; - List : Iir_List; begin Res (Off) := '<'; Off := Off + 1; - List := Get_Elements_Declaration_List (Get_Base_Type (Def)); - for I in Natural loop + for I in Flist_First .. Flist_Last (List) loop El := Get_Nth_Element (List, I); - exit when El = Null_Iir; Get_File_Signature (Get_Type (El), Res, Off); end loop; Res (Off) := '>'; @@ -371,22 +369,21 @@ package body Annotations is when Iir_Kind_Array_Subtype_Definition => declare - List : constant Iir_List := Get_Index_Subtype_List (Def); + List : constant Iir_Flist := Get_Index_Subtype_List (Def); begin - for I in Natural loop + for I in Flist_First .. Flist_Last (List) loop El := Get_Index_Type (List, I); - exit when El = Null_Iir; Annotate_Anonymous_Type_Definition (Block_Info, El); end loop; end; when Iir_Kind_Record_Type_Definition => declare - List : constant Iir_List := Get_Elements_Declaration_List (Def); + List : constant Iir_Flist := + Get_Elements_Declaration_List (Def); begin - for I in Natural loop + for I in Flist_First .. Flist_Last (List) loop El := Get_Nth_Element (List, I); - exit when El = Null_Iir; Annotate_Anonymous_Type_Definition (Block_Info, Get_Type (El)); end loop; diff --git a/src/vhdl/simulate/debugger.adb b/src/vhdl/simulate/debugger.adb index 75f099c8e..977e6e3a3 100644 --- a/src/vhdl/simulate/debugger.adb +++ b/src/vhdl/simulate/debugger.adb @@ -348,10 +348,10 @@ package body Debugger is procedure Disp_Signal_Record (Value : Iir_Value_Literal_Acc; A_Type : Iir) is + List : constant Iir_Flist := + Get_Elements_Declaration_List (Get_Base_Type (A_Type)); El : Iir_Element_Declaration; - List : Iir_List; begin - List := Get_Elements_Declaration_List (Get_Base_Type (A_Type)); Put ("("); for I in Value.Val_Record.V'Range loop El := Get_Nth_Element (List, Natural (I - 1)); diff --git a/src/vhdl/simulate/elaboration.adb b/src/vhdl/simulate/elaboration.adb index ef5db6bdb..cb777b727 100644 --- a/src/vhdl/simulate/elaboration.adb +++ b/src/vhdl/simulate/elaboration.adb @@ -631,16 +631,15 @@ package body Elaboration is when Iir_Kind_Record_Type_Definition | Iir_Kind_Record_Subtype_Definition => declare - El : Iir_Element_Declaration; - List : constant Iir_List := + List : constant Iir_Flist := Get_Elements_Declaration_List (Get_Base_Type (Decl)); + El : Iir_Element_Declaration; begin Res := Create_Record_Value (Iir_Index32 (Get_Nbr_Elements (List))); - for I in Natural loop + for I in Flist_First .. Flist_Last (List) loop El := Get_Nth_Element (List, I); - exit when El = Null_Iir; Res.Val_Record.V (1 + Get_Element_Position (El)) := Create_Value_For_Type (Block, Get_Type (El), Init); end loop; @@ -687,13 +686,12 @@ package body Elaboration is when Iir_Kind_Record_Type_Definition | Iir_Kind_Record_Subtype_Definition => declare - El : Iir_Element_Declaration; - List : constant Iir_List := + List : constant Iir_Flist := Get_Elements_Declaration_List (Get_Base_Type (Atype)); + El : Iir_Element_Declaration; begin - for I in Natural loop + for I in Flist_First .. Flist_Last (List) loop El := Get_Nth_Element (List, I); - exit when El = Null_Iir; Init_To_Default (Targ.Val_Record.V (1 + Iir_Index32 (I)), Block, Get_Type (El)); end loop; @@ -882,12 +880,11 @@ package body Elaboration is -- declaration of each of the discrete ranges in the index -- constraint in some order that is not defined by the language. declare - St_Indexes : constant Iir_List := Get_Index_Subtype_List (Ind); + St_Indexes : constant Iir_Flist := Get_Index_Subtype_List (Ind); St_El : Iir; begin - for I in Natural loop + for I in Flist_First .. Flist_Last (St_Indexes) loop St_El := Get_Index_Type (St_Indexes, I); - exit when St_El = Null_Iir; Elaborate_Subtype_Indication_If_Anonymous (Instance, St_El); end loop; Elaborate_Subtype_Indication_If_Anonymous @@ -952,13 +949,12 @@ package body Elaboration is -- elaboration of the equivalent single element declarations in -- the given order. declare + List : constant Iir_Flist := + Get_Elements_Declaration_List (Def); El : Iir_Element_Declaration; - List : Iir_List; begin - List := Get_Elements_Declaration_List (Def); - for I in Natural loop + for I in Flist_First .. Flist_Last (List) loop El := Get_Nth_Element (List, I); - exit when El = Null_Iir; -- Elaboration of an element declaration consists of -- elaboration of the element subtype indication. Elaborate_Subtype_Indication_If_Anonymous @@ -2095,13 +2091,13 @@ package body Elaboration is (Item, Sub_Instances (Ind + I - 1)); end loop; when Iir_Kind_Indexed_Name => - if Get_Index_List (Spec) = Iir_List_Others then + if Get_Index_List (Spec) = Iir_Flist_Others then -- Must be the only default block configuration pragma Assert (Default_Item = Null_Iir); Default_Item := Item; else Expr := Execute_Expression - (Instance, Get_First_Element (Get_Index_List (Spec))); + (Instance, Get_Nth_Element (Get_Index_List (Spec), 0)); Ind := Instance_Slot_Type (Get_Index_Offset (Expr, Bounds, Spec)); Sub_Conf (Ind) := True; @@ -2215,17 +2211,16 @@ package body Elaboration is when Iir_Kind_Component_Configuration => declare - List : constant Iir_List := + List : constant Iir_Flist := Get_Instantiation_List (Item); El : Iir; Info : Sim_Info_Acc; begin - if List = Iir_List_All or else List = Iir_List_Others then + if List = Iir_Flist_All or else List = Iir_Flist_Others then raise Internal_Error; end if; - for I in Natural loop + for I in Flist_First .. Flist_Last (List) loop El := Get_Nth_Element (List, I); - exit when El = Null_Iir; Info := Get_Info (Get_Named_Entity (El)); pragma Assert (Sub_Conf (Info.Inst_Slot) = Null_Iir); Sub_Conf (Info.Inst_Slot) := Item; @@ -2310,7 +2305,7 @@ package body Elaboration is is Time_Val : Iir_Value_Literal_Acc; Time : Iir_Value_Time; - List : Iir_List; + List : Iir_Flist; Sig : Iir; Val : Iir_Value_Literal_Acc; begin @@ -2339,13 +2334,12 @@ package body Elaboration is -- signals. List := Get_Signal_List (Decl); case List is - when Iir_List_All - | Iir_List_Others => + when Iir_Flist_All + | Iir_Flist_Others => Error_Kind ("elaborate_disconnection_specification", Decl); when others => - for I in Natural loop + for I in Flist_First .. Flist_Last (List) loop Sig := Get_Nth_Element (List, I); - exit when Sig = Null_Iir; Val := Execute_Name (Instance, Sig, True); Disconnection_Table.Append ((Sig => Val, Time => Time)); end loop; diff --git a/src/vhdl/simulate/execution.adb b/src/vhdl/simulate/execution.adb index ad15360f9..f5aa56073 100644 --- a/src/vhdl/simulate/execution.adb +++ b/src/vhdl/simulate/execution.adb @@ -278,7 +278,7 @@ package body Execution is when Iir_Kind_Enumeration_Type_Definition | Iir_Kind_Enumeration_Subtype_Definition => declare - Lits : constant Iir_List := + Lits : constant Iir_Flist := Get_Enumeration_Literal_List (Get_Base_Type (Expr_Type)); Pos : Natural; begin @@ -682,7 +682,7 @@ package body Execution is Result := Create_Array_Value (Len, 1); Result.Bounds.D (1) := Create_Bounds_From_Length (Block, - Get_First_Element (Get_Index_Subtype_List (Res_Type)), + Get_Nth_Element (Get_Index_Subtype_List (Res_Type), 0), Len); end if; @@ -1275,7 +1275,7 @@ package body Execution is use Name_Table; Base_Type : constant Iir := Get_Base_Type (Get_Type (Left_Param)); - Lits : constant Iir_List := + Lits : constant Iir_Flist := Get_Enumeration_Literal_List (Base_Type); Pos : constant Natural := Get_Enum_Pos (Left); Id : Name_Id; @@ -1319,11 +1319,11 @@ package body Execution is when Iir_Predefined_Array_Char_To_String => declare - Str : String (1 .. Natural (Left.Bounds.D (1).Length)); - Lits : constant Iir_List := + Lits : constant Iir_Flist := Get_Enumeration_Literal_List (Get_Base_Type (Get_Element_Subtype (Get_Type (Left_Param)))); + Str : String (1 .. Natural (Left.Bounds.D (1).Length)); Pos : Natural; begin for I in Left.Val_Array.V'Range loop @@ -1667,15 +1667,14 @@ package body Execution is Create_Val_Array : Boolean) return Iir_Value_Literal_Acc is + -- Only for constrained subtypes. + pragma Assert (Get_Kind (A_Type) /= Iir_Kind_Array_Type_Definition); + + Index_List : constant Iir_Flist := Get_Index_Subtype_List (A_Type); Res : Iir_Value_Literal_Acc; - Index_List : Iir_List; Len : Iir_Index32; Bound : Iir_Value_Literal_Acc; begin - -- Only for constrained subtypes. - pragma Assert (Get_Kind (A_Type) /= Iir_Kind_Array_Type_Definition); - - Index_List := Get_Index_Subtype_List (A_Type); Res := Create_Array_Value (Iir_Index32 (Get_Nbr_Elements (Index_List))); Len := 1; @@ -1749,9 +1748,9 @@ package body Execution is function String_To_Enumeration_Array (Block: Block_Instance_Acc; Str: Iir) return Iir_Value_Literal_Acc is - Res : Iir_Value_Literal_Acc; Array_Type: constant Iir := Get_Type (Str); - Index_Types : constant Iir_List := Get_Index_Subtype_List (Array_Type); + Index_Types : constant Iir_Flist := Get_Index_Subtype_List (Array_Type); + Res : Iir_Value_Literal_Acc; begin -- Array must be unidimensional. pragma Assert (Get_Nbr_Elements (Index_Types) = 1); @@ -1769,7 +1768,7 @@ package body Execution is Res.Val_Array.Len); else Res.Bounds.D (1) := - Execute_Bounds (Block, Get_First_Element (Index_Types)); + Execute_Bounds (Block, Get_Nth_Element (Index_Types, 0)); end if; -- The range may not be statically constant. @@ -1939,7 +1938,7 @@ package body Execution is is Aggr_Type : constant Iir := Get_Type (Aggregate); El_Type : constant Iir := Get_Element_Subtype (Aggr_Type); - Index_List : constant Iir_List := Get_Index_Subtype_List (Aggr_Type); + Index_List : constant Iir_Flist := Get_Index_Subtype_List (Aggr_Type); Nbr_Dim : constant Iir_Index32 := Iir_Index32 (Get_Nbr_Elements (Index_List)); Step : Iir_Index32; @@ -1954,7 +1953,7 @@ package body Execution is Aggregate_Type: Iir) return Iir_Value_Literal_Acc is - List : constant Iir_List := + List : constant Iir_Flist := Get_Elements_Declaration_List (Get_Base_Type (Aggregate_Type)); Res: Iir_Value_Literal_Acc; @@ -2031,7 +2030,7 @@ package body Execution is return Iir_Value_Literal_Acc is Res : Iir_Value_Literal_Acc; - List : constant Iir_List := Get_Simple_Aggregate_List (Aggr); + List : constant Iir_Flist := Get_Simple_Aggregate_List (Aggr); begin Res := Create_Array_Bounds_From_Type (Block, Get_Type (Aggr), True); for I in Res.Val_Array.V'Range loop @@ -2111,7 +2110,7 @@ package body Execution is Aggregate_Type: Iir) return Iir_Value_Literal_Acc is - List : constant Iir_List := + List : constant Iir_Flist := Get_Elements_Declaration_List (Get_Base_Type (Aggregate_Type)); Res: Iir_Value_Literal_Acc; Expr : Iir; @@ -2159,12 +2158,12 @@ package body Execution is when Iir_Kind_Array_Type_Definition | Iir_Kind_Array_Subtype_Definition => declare - Res : Iir_Value_Literal_Acc; El_Type : constant Iir := Get_Element_Subtype (Aggregate_Type); - Index_List : constant Iir_List := + Index_List : constant Iir_Flist := Get_Index_Subtype_List (Aggregate_Type); Nbr_Dim : constant Iir_Index32 := Iir_Index32 (Get_Nbr_Elements (Index_List)); + Res : Iir_Value_Literal_Acc; Step : Iir_Index32; begin Res := Create_Array_Bounds_From_Type @@ -2344,7 +2343,7 @@ package body Execution is Implicit_Array_Conversion (Block, Res, Target_Type, Loc); else declare - Idx_List : constant Iir_List := + Idx_List : constant Iir_Flist := Get_Index_Subtype_List (Target_Type); Idx_Type : Iir; begin @@ -2482,7 +2481,7 @@ package body Execution is Pos : out Iir_Index32) is pragma Assert (Get_Kind (Expr) = Iir_Kind_Indexed_Name); - Index_List : constant Iir_List := Get_Index_List (Expr); + Index_List : constant Iir_Flist := Get_Index_List (Expr); Nbr_Dimensions : constant Iir_Index32 := Iir_Index32 (Get_Nbr_Elements (Index_List)); Index: Iir; @@ -2777,10 +2776,10 @@ package body Execution is when Iir_Kind_Enumeration_Type_Definition | Iir_Kind_Enumeration_Subtype_Definition => declare + Enums : constant Iir_Flist := + Get_Enumeration_Literal_List (Get_Base_Type (Expr_Type)); Lit_Start : Ghdl_Index_Type; Lit_End : Ghdl_Index_Type; - Enums : constant Iir_List := - Get_Enumeration_Literal_List (Get_Base_Type (Expr_Type)); Enum : Iir; Lit_Id : Name_Id; Enum_Id : Name_Id; @@ -3822,8 +3821,8 @@ package body Execution is Def: Iir; Expr: Iir) is - Index_List: Iir_List; - Element_Subtype: Iir; + Index_List : Iir_Flist; + Element_Subtype : Iir; New_Bounds : Iir_Value_Literal_Acc; begin -- Nothing to check for unconstrained arrays. @@ -3922,13 +3921,12 @@ package body Execution is when Iir_Kind_Record_Type_Definition | Iir_Kind_Record_Subtype_Definition => declare - El: Iir_Element_Declaration; - List : Iir_List; + List : constant Iir_Flist := + Get_Elements_Declaration_List (Get_Base_Type (Def)); + El : Iir_Element_Declaration; begin - List := Get_Elements_Declaration_List (Get_Base_Type (Def)); - for I in Natural loop + for I in Flist_First .. Flist_Last (List) loop El := Get_Nth_Element (List, I); - exit when El = Null_Iir; Check_Constraints (Instance, Value.Val_Record.V (Get_Element_Position (El) + 1), diff --git a/src/vhdl/simulate/iir_values.adb b/src/vhdl/simulate/iir_values.adb index 6723b2043..019392b02 100644 --- a/src/vhdl/simulate/iir_values.adb +++ b/src/vhdl/simulate/iir_values.adb @@ -959,7 +959,7 @@ package body Iir_Values is type Last_Enum_Type is (None, Char, Identifier); Last_Enum: Last_Enum_Type; El_Type: Iir; - Enum_List: Iir_List; + Enum_List: Iir_Flist; El_Id : Name_Id; El_Pos : Natural; begin @@ -1036,10 +1036,10 @@ package body Iir_Values is (Value: Iir_Value_Literal_Acc; A_Type: Iir) is use Ada.Text_IO; + List : constant Iir_Flist := + Get_Elements_Declaration_List (Get_Base_Type (A_Type)); El : Iir_Element_Declaration; - List : Iir_List; begin - List := Get_Elements_Declaration_List (Get_Base_Type (A_Type)); Put ("("); for I in Value.Val_Record.V'Range loop El := Get_Nth_Element (List, Natural (I - 1)); diff --git a/src/vhdl/simulate/simulation-main.adb b/src/vhdl/simulate/simulation-main.adb index 3466c9d43..cc46df813 100644 --- a/src/vhdl/simulate/simulation-main.adb +++ b/src/vhdl/simulate/simulation-main.adb @@ -997,11 +997,10 @@ package body Simulation.Main is end; when Iir_Value_Record => declare + List : constant Iir_Flist := Get_Elements_Declaration_List + (Get_Base_Type (Sig_Type)); El : Iir_Element_Declaration; - List : Iir_List; begin - List := Get_Elements_Declaration_List - (Get_Base_Type (Sig_Type)); for I in Val.Val_Record.V'Range loop El := Get_Nth_Element (List, Natural (I - 1)); Create_Signal (Val.Val_Record.V (I), Sig.Val_Record.V (I), diff --git a/src/vhdl/simulate/simulation.adb b/src/vhdl/simulate/simulation.adb index 0b01a4c88..52dc894d2 100644 --- a/src/vhdl/simulate/simulation.adb +++ b/src/vhdl/simulate/simulation.adb @@ -659,7 +659,7 @@ package body Simulation is Arr := Create_Array_Value (Len, 1); Arr.Bounds.D (1) := Create_Bounds_From_Length (Instance.Block, - Get_First_Element (Get_Index_Subtype_List (Arr_Type)), + Get_Nth_Element (Get_Index_Subtype_List (Arr_Type), 0), Len); -- First ports |