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-rw-r--r--src/vhdl/simulate/simulation-main.adb5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/vhdl/simulate/simulation-main.adb b/src/vhdl/simulate/simulation-main.adb
index 3466c9d43..cc46df813 100644
--- a/src/vhdl/simulate/simulation-main.adb
+++ b/src/vhdl/simulate/simulation-main.adb
@@ -997,11 +997,10 @@ package body Simulation.Main is
end;
when Iir_Value_Record =>
declare
+ List : constant Iir_Flist := Get_Elements_Declaration_List
+ (Get_Base_Type (Sig_Type));
El : Iir_Element_Declaration;
- List : Iir_List;
begin
- List := Get_Elements_Declaration_List
- (Get_Base_Type (Sig_Type));
for I in Val.Val_Record.V'Range loop
El := Get_Nth_Element (List, Natural (I - 1));
Create_Signal (Val.Val_Record.V (I), Sig.Val_Record.V (I),