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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-25 15:15:48 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-25 15:15:48 +0200 |
| commit | 551fe31c9a9331998199369f903ede9c3cb4a79c (patch) | |
| tree | a0eaa704100872c10430e05981be137b3dc70bab /src/vhdl | |
| parent | 8e56ee72b5095412f0de3d358668f41579c1194e (diff) | |
| download | ghdl-551fe31c9a9331998199369f903ede9c3cb4a79c.tar.gz ghdl-551fe31c9a9331998199369f903ede9c3cb4a79c.tar.bz2 ghdl-551fe31c9a9331998199369f903ede9c3cb4a79c.zip | |
synth: rework error procedure, always pass the instance
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/vhdl-evaluation.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vhdl/vhdl-evaluation.adb b/src/vhdl/vhdl-evaluation.adb index c4cbcae50..65e12cabe 100644 --- a/src/vhdl/vhdl-evaluation.adb +++ b/src/vhdl/vhdl-evaluation.adb @@ -1035,10 +1035,10 @@ package body Vhdl.Evaluation is if Right /= Null_Iir then Right_Mt := Convert_Node_To_Memtyp (Right); Res_Mt := Eval_Static_Dyadic_Predefined - (Imp, Res_Typ, Left_Mt, Right_Mt, Orig); + (null, Imp, Res_Typ, Left_Mt, Right_Mt, Orig); else Res_Mt := Eval_Static_Monadic_Predefined - (Imp, Left_Mt, Orig); + (null, Imp, Left_Mt, Orig); end if; Res := Convert_Memtyp_To_Node (Res_Mt, Res_Type, Orig); Release_Expr_Pool (Marker); |