17 files changed, 406 insertions, 254 deletions
diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb
index 6a6140cee..0a752dc22 100644
--- a/src/ghdldrv/ghdlsimul.adb
+++ b/src/ghdldrv/ghdlsimul.adb
@@ -47,6 +47,7 @@ with Elab.Vhdl_Insts;
 with Elab.Debugger;
 
 with Synth.Flags;
+with Synth.Errors;
 with Simul.Vhdl_Elab;
 with Simul.Vhdl_Simul;
 
@@ -88,6 +89,7 @@ package body Ghdlsimul is
       end loop;
 
       Synth.Flags.Flag_Simulation := True;
+      Synth.Errors.Debug_Handler := Elab.Debugger.Debug_Error'Access;
 
       Lib_Unit := Get_Library_Unit (Config);
       pragma Assert (Get_Kind (Lib_Unit) /= Iir_Kind_Foreign_Module);
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index cae02fad7..f7a51b822 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -743,7 +743,7 @@ package body Simul.Vhdl_Simul is
          begin
             if Get_Foreign_Flag (Imp) then
                Synth.Errors.Error_Msg_Synth
-                 (+Stmt, "call to foreign %n is not supported", +Imp);
+                 (Inst, Stmt, "call to foreign %n is not supported", +Imp);
                Next_Stmt := Null_Node;
                return;
             end if;
diff --git a/src/synth/netlists-inference.adb b/src/synth/netlists-inference.adb
index 4f3440d74..2c50648e9 100644
--- a/src/synth/netlists-inference.adb
+++ b/src/synth/netlists-inference.adb
@@ -391,7 +391,7 @@ package body Netlists.Inference is
             end if;
          else
             if Els_Net /= No_Net then
-               Error_Msg_Synth
+               Error_Msg_Netlist
                  (Loc, "synchronous code does not expect else part");
             end if;
 
@@ -447,7 +447,7 @@ package body Netlists.Inference is
             Els_Clk := No_Net;
          end if;
          if Els_Clk = No_Net then
-            Error_Msg_Synth
+            Error_Msg_Netlist
               (Mux_Loc, "clocked logic requires clocked logic on else part");
             Els := No_Net;
          else
@@ -856,8 +856,8 @@ package body Netlists.Inference is
             Name := Get_Instance_Name (Get_Net_Parent (Prev_Val));
          end if;
 
-         Error_Msg_Synth
-           (Loc, "latch infered for net %n (use --latches)", +Name);
+         Error_Msg_Netlist
+           (Loc, "latch infered for net %n (use --latches)", (1 => +Name));
       end if;
 
       if False then
@@ -1058,7 +1058,7 @@ package body Netlists.Inference is
       begin
          Next_Inst := Find_Condition_Chain_Next (Last_Inst);
          if Next_Inst /= Get_Net_Parent (Get_Input_Net (Inst, 2)) then
-            Error_Msg_Synth
+            Error_Msg_Netlist
               (+Last_Inst, "assertion checked on else branch of an edge");
             return Val;
          end if;
diff --git a/src/synth/synth-errors.adb b/src/synth/synth-errors.adb
index a0b672770..795c0e1c4 100644
--- a/src/synth/synth-errors.adb
+++ b/src/synth/synth-errors.adb
@@ -17,20 +17,41 @@
 --  along with this program.  If not, see <gnu.org/licenses>.
 
 package body Synth.Errors is
-   procedure Error_Msg_Synth (Loc : Location_Type;
+   procedure Error_Msg_Netlist (Loc : Location_Type;
+                                Msg : String;
+                                Args : Earg_Arr := No_Eargs) is
+   begin
+      Report_Msg (Msgid_Error, Errorout.Elaboration,
+                  +Loc, Msg, Args);
+   end Error_Msg_Netlist;
+
+   function To_Coord (N : Node) return Source_Coord_Type is
+   begin
+      return +Get_Location (N);
+   end To_Coord;
+
+   procedure Error_Msg_Synth (Inst : Synth_Instance_Acc;
+                              Loc : Node;
                               Msg : String;
                               Arg1 : Earg_Type) is
    begin
       Report_Msg (Msgid_Error, Errorout.Elaboration,
-                  +Loc, Msg, (1 => Arg1));
+                  To_Coord (Loc), Msg, (1 => Arg1));
+      if Inst /= null and then Debug_Handler /= null then
+         Debug_Handler (Inst, Loc);
+      end if;
    end Error_Msg_Synth;
 
-   procedure Error_Msg_Synth (Loc : Location_Type;
+   procedure Error_Msg_Synth (Inst : Synth_Instance_Acc;
+                              Loc : Node;
                               Msg : String;
                               Args : Earg_Arr := No_Eargs) is
    begin
       Report_Msg (Msgid_Error, Errorout.Elaboration,
-                  +Loc, Msg, Args);
+                  To_Coord (Loc), Msg, Args);
+      if Inst /= null and then Debug_Handler /= null then
+         Debug_Handler (Inst, Loc);
+      end if;
    end Error_Msg_Synth;
 
    procedure Warning_Msg_Synth (Warnid : Msgid_Warnings;
diff --git a/src/synth/synth-errors.ads b/src/synth/synth-errors.ads
index 448ab6be1..c238d7575 100644
--- a/src/synth/synth-errors.ads
+++ b/src/synth/synth-errors.ads
@@ -19,13 +19,26 @@
 with Types; use Types;
 with Errorout; use Errorout;
 
+with Vhdl.Nodes; use Vhdl.Nodes;
+with Elab.Vhdl_Context; use Elab.Vhdl_Context;
+
 package Synth.Errors is
-   procedure Error_Msg_Synth (Loc : Location_Type;
+   --  The error procedures return during synthesis, but not during
+   --  simulation (they are fatal).
+   --  Debugger may be called.
+   procedure Error_Msg_Synth (Inst : Synth_Instance_Acc;
+                              Loc : Node;
                               Msg : String;
                               Arg1 : Earg_Type);
-   procedure Error_Msg_Synth (Loc : Location_Type;
+   procedure Error_Msg_Synth (Inst : Synth_Instance_Acc;
+                              Loc : Node;
                               Msg : String;
                               Args : Earg_Arr := No_Eargs);
+
+   procedure Error_Msg_Netlist (Loc : Location_Type;
+                                Msg : String;
+                                Args : Earg_Arr := No_Eargs);
+
    procedure Warning_Msg_Synth (Warnid : Msgid_Warnings;
                                 Loc : Location_Type;
                                 Msg : String;
@@ -36,4 +49,8 @@ package Synth.Errors is
    procedure Info_Msg_Synth (Loc : Location_Type;
                              Msg : String;
                              Args : Earg_Arr := No_Eargs);
+
+   type Handler_Access is access procedure (Inst : Synth_Instance_Acc;
+                                            Loc : Node);
+   Debug_Handler : Handler_Access;
 end Synth.Errors;
diff --git a/src/synth/synth-ieee-numeric_std.adb b/src/synth/synth-ieee-numeric_std.adb
index 7a5ce751d..ff0a2fb28 100644
--- a/src/synth/synth-ieee-numeric_std.adb
+++ b/src/synth/synth-ieee-numeric_std.adb
@@ -22,6 +22,7 @@ with Elab.Memtype; use Elab.Memtype;
 
 with Synth.Errors; use Synth.Errors;
 with Synth.Ieee.Utils; use Synth.Ieee.Utils;
+with Synth.Source; use Synth.Source;
 
 package body Synth.Ieee.Numeric_Std is
 
@@ -1088,7 +1089,9 @@ package body Synth.Ieee.Numeric_Std is
       end if;
    end Divmod;
 
-   function Div_Uns_Uns (L, R : Memtyp; Loc : Location_Type) return Memtyp
+   function Div_Uns_Uns (Inst : Synth_Instance_Acc;
+                         L, R : Memtyp;
+                         Loc : Node) return Memtyp
    is
       Nlen  : constant Uns32 := L.Typ.Abound.Len;
       Dlen  : constant Uns32 := R.Typ.Abound.Len;
@@ -1109,7 +1112,7 @@ package body Synth.Ieee.Numeric_Std is
          return Quot;
       end if;
       if R0 = '0' then
-         Error_Msg_Synth (+Loc, "NUMERIC_STD.""/"": division by 0");
+         Error_Msg_Synth (Inst, Loc, "NUMERIC_STD.""/"": division by 0");
          Fill (Quot, 'X');
          return Quot;
       end if;
@@ -1117,8 +1120,10 @@ package body Synth.Ieee.Numeric_Std is
       return Quot;
    end Div_Uns_Uns;
 
-   function Div_Uns_Nat (L : Memtyp; R : Uns64; Loc : Location_Type)
-                        return Memtyp
+   function Div_Uns_Nat (Inst : Synth_Instance_Acc;
+                         L : Memtyp;
+                         R : Uns64;
+                         Loc : Node) return Memtyp
    is
       Rv : Memtyp;
    begin
@@ -1126,11 +1131,13 @@ package body Synth.Ieee.Numeric_Std is
          return Create_Memory (L.Typ); --  FIXME: typ
       end if;
       Rv := To_Unsigned (R, L.Typ);
-      return Div_Uns_Uns (L, Rv, Loc);
+      return Div_Uns_Uns (Inst, L, Rv, Loc);
    end Div_Uns_Nat;
 
-   function Div_Nat_Uns (L : Uns64; R : Memtyp; Loc : Location_Type)
-                        return Memtyp
+   function Div_Nat_Uns (Inst : Synth_Instance_Acc;
+                         L : Uns64;
+                         R : Memtyp;
+                         Loc : Node) return Memtyp
    is
       Lv : Memtyp;
    begin
@@ -1138,10 +1145,12 @@ package body Synth.Ieee.Numeric_Std is
          return Create_Memory (R.Typ); --  FIXME: typ
       end if;
       Lv := To_Unsigned (L, R.Typ);
-      return Div_Uns_Uns (Lv, R, Loc);
+      return Div_Uns_Uns (Inst, Lv, R, Loc);
    end Div_Nat_Uns;
 
-   function Div_Sgn_Sgn (L, R : Memtyp; Loc : Location_Type) return Memtyp
+   function Div_Sgn_Sgn (Inst : Synth_Instance_Acc;
+                         L, R : Memtyp;
+                         Loc : Node) return Memtyp
    is
       Nlen  : constant Uns32 := L.Typ.Abound.Len;
       Dlen  : constant Uns32 := R.Typ.Abound.Len;
@@ -1165,7 +1174,7 @@ package body Synth.Ieee.Numeric_Std is
          return Quot;
       end if;
       if R0 = '0' then
-         Error_Msg_Synth (+Loc, "NUMERIC_STD.""/"": division by 0");
+         Error_Msg_Synth (Inst, Loc, "NUMERIC_STD.""/"": division by 0");
          Fill (Quot, 'X');
          return Quot;
       end if;
@@ -1195,8 +1204,10 @@ package body Synth.Ieee.Numeric_Std is
       return Quot;
    end Div_Sgn_Sgn;
 
-   function Div_Sgn_Int (L : Memtyp; R : Int64; Loc : Location_Type)
-                        return Memtyp
+   function Div_Sgn_Int (Inst : Synth_Instance_Acc;
+                         L : Memtyp;
+                         R : Int64;
+                         Loc : Node) return Memtyp
    is
       Rv : Memtyp;
    begin
@@ -1204,11 +1215,13 @@ package body Synth.Ieee.Numeric_Std is
          return Create_Memory (L.Typ); --  FIXME: typ
       end if;
       Rv := To_Signed (R, L.Typ);
-      return Div_Sgn_Sgn (L, Rv, Loc);
+      return Div_Sgn_Sgn (Inst, L, Rv, Loc);
    end Div_Sgn_Int;
 
-   function Div_Int_Sgn (L : Int64; R : Memtyp; Loc : Location_Type)
-                        return Memtyp
+   function Div_Int_Sgn (Inst : Synth_Instance_Acc;
+                         L : Int64;
+                         R : Memtyp;
+                         Loc : Node) return Memtyp
    is
       Lv : Memtyp;
    begin
@@ -1216,10 +1229,12 @@ package body Synth.Ieee.Numeric_Std is
          return Create_Memory (R.Typ); --  FIXME: typ
       end if;
       Lv := To_Signed (L, R.Typ);
-      return Div_Sgn_Sgn (Lv, R, Loc);
+      return Div_Sgn_Sgn (Inst, Lv, R, Loc);
    end Div_Int_Sgn;
 
-   function Rem_Uns_Uns (L, R : Memtyp; Loc : Location_Type) return Memtyp
+   function Rem_Uns_Uns (Inst : Synth_Instance_Acc;
+                         L, R : Memtyp;
+                         Loc : Node) return Memtyp
    is
       Nlen  : constant Uns32 := L.Typ.Abound.Len;
       Dlen  : constant Uns32 := R.Typ.Abound.Len;
@@ -1240,7 +1255,7 @@ package body Synth.Ieee.Numeric_Std is
          return Rema;
       end if;
       if R0 = '0' then
-         Error_Msg_Synth (+Loc, "NUMERIC_STD.""rem"": division by 0");
+         Error_Msg_Synth (Inst, Loc, "NUMERIC_STD.""rem"": division by 0");
          Fill (Rema, 'X');
          return Rema;
       end if;
@@ -1248,8 +1263,10 @@ package body Synth.Ieee.Numeric_Std is
       return Rema;
    end Rem_Uns_Uns;
 
-   function Rem_Uns_Nat (L : Memtyp; R : Uns64; Loc : Location_Type)
-                        return Memtyp
+   function Rem_Uns_Nat (Inst : Synth_Instance_Acc;
+                         L : Memtyp;
+                         R : Uns64;
+                         Loc : Node) return Memtyp
    is
       Rv : Memtyp;
    begin
@@ -1257,11 +1274,13 @@ package body Synth.Ieee.Numeric_Std is
          return Create_Memory (L.Typ); --  FIXME: typ
       end if;
       Rv := To_Unsigned (R, L.Typ);
-      return Rem_Uns_Uns (L, Rv, Loc);
+      return Rem_Uns_Uns (Inst, L, Rv, Loc);
    end Rem_Uns_Nat;
 
-   function Rem_Nat_Uns (L : Uns64; R : Memtyp; Loc : Location_Type)
-                        return Memtyp
+   function Rem_Nat_Uns (Inst : Synth_Instance_Acc;
+                         L : Uns64;
+                         R : Memtyp;
+                         Loc : Node) return Memtyp
    is
       Lv : Memtyp;
    begin
@@ -1269,10 +1288,12 @@ package body Synth.Ieee.Numeric_Std is
          return Create_Memory (R.Typ); --  FIXME: typ
       end if;
       Lv := To_Unsigned (L, R.Typ);
-      return Rem_Uns_Uns (Lv, R, Loc);
+      return Rem_Uns_Uns (Inst, Lv, R, Loc);
    end Rem_Nat_Uns;
 
-   function Rem_Sgn_Sgn (L, R : Memtyp; Loc : Location_Type) return Memtyp
+   function Rem_Sgn_Sgn (Inst : Synth_Instance_Acc;
+                         L, R : Memtyp;
+                         Loc : Node) return Memtyp
    is
       Nlen  : constant Uns32 := L.Typ.Abound.Len;
       Dlen  : constant Uns32 := R.Typ.Abound.Len;
@@ -1296,7 +1317,7 @@ package body Synth.Ieee.Numeric_Std is
          return Rema;
       end if;
       if R0 = '0' then
-         Error_Msg_Synth (+Loc, "NUMERIC_STD.""rem"": division by 0");
+         Error_Msg_Synth (Inst, Loc, "NUMERIC_STD.""rem"": division by 0");
          Fill (Rema, 'X');
          return Rema;
       end if;
@@ -1326,8 +1347,10 @@ package body Synth.Ieee.Numeric_Std is
       return Rema;
    end Rem_Sgn_Sgn;
 
-   function Rem_Sgn_Int (L : Memtyp; R : Int64; Loc : Location_Type)
-                        return Memtyp
+   function Rem_Sgn_Int (Inst : Synth_Instance_Acc;
+                         L : Memtyp;
+                         R : Int64;
+                         Loc : Node) return Memtyp
    is
       Rv : Memtyp;
    begin
@@ -1335,11 +1358,13 @@ package body Synth.Ieee.Numeric_Std is
          return Create_Memory (L.Typ); --  FIXME: typ
       end if;
       Rv := To_Signed (R, L.Typ);
-      return Rem_Sgn_Sgn (L, Rv, Loc);
+      return Rem_Sgn_Sgn (Inst, L, Rv, Loc);
    end Rem_Sgn_Int;
 
-   function Rem_Int_Sgn (L : Int64; R : Memtyp; Loc : Location_Type)
-                        return Memtyp
+   function Rem_Int_Sgn (Inst : Synth_Instance_Acc;
+                         L : Int64;
+                         R : Memtyp;
+                         Loc : Node) return Memtyp
    is
       Lv : Memtyp;
    begin
@@ -1347,10 +1372,12 @@ package body Synth.Ieee.Numeric_Std is
          return Create_Memory (R.Typ); --  FIXME: typ
       end if;
       Lv := To_Signed (L, R.Typ);
-      return Rem_Sgn_Sgn (Lv, R, Loc);
+      return Rem_Sgn_Sgn (Inst, Lv, R, Loc);
    end Rem_Int_Sgn;
 
-   function Mod_Sgn_Sgn (L, R : Memtyp; Loc : Location_Type) return Memtyp
+   function Mod_Sgn_Sgn (Inst : Synth_Instance_Acc;
+                         L, R : Memtyp;
+                         Loc : Node) return Memtyp
    is
       Nlen  : constant Uns32 := L.Typ.Abound.Len;
       Dlen  : constant Uns32 := R.Typ.Abound.Len;
@@ -1374,7 +1401,7 @@ package body Synth.Ieee.Numeric_Std is
          return Rema;
       end if;
       if R0 = '0' then
-         Error_Msg_Synth (+Loc, "NUMERIC_STD.""rem"": division by 0");
+         Error_Msg_Synth (Inst, Loc, "NUMERIC_STD.""rem"": division by 0");
          Fill (Rema, 'X');
          return Rema;
       end if;
@@ -1409,11 +1436,11 @@ package body Synth.Ieee.Numeric_Std is
                Neg_Vec (Rema);
                return Rema;
             else
-               return Add_Vec_Vec (R, Rema, True, Loc);
+               return Add_Vec_Vec (R, Rema, True, +Loc);
             end if;
          else
             if L_Neg then
-               return Sub_Vec_Vec (R, Rema, True, Loc);
+               return Sub_Vec_Vec (R, Rema, True, +Loc);
             else
                return Rema;
             end if;
@@ -1421,8 +1448,10 @@ package body Synth.Ieee.Numeric_Std is
       end if;
    end Mod_Sgn_Sgn;
 
-   function Mod_Sgn_Int (L : Memtyp; R : Int64; Loc : Location_Type)
-                        return Memtyp
+   function Mod_Sgn_Int (Inst : Synth_Instance_Acc;
+                         L : Memtyp;
+                         R : Int64;
+                         Loc : Node) return Memtyp
    is
       Rv : Memtyp;
    begin
@@ -1430,11 +1459,13 @@ package body Synth.Ieee.Numeric_Std is
          return Create_Memory (L.Typ); --  FIXME: typ
       end if;
       Rv := To_Signed (R, L.Typ);
-      return Mod_Sgn_Sgn (L, Rv, Loc);
+      return Mod_Sgn_Sgn (Inst, L, Rv, Loc);
    end Mod_Sgn_Int;
 
-   function Mod_Int_Sgn (L : Int64; R : Memtyp; Loc : Location_Type)
-                        return Memtyp
+   function Mod_Int_Sgn (Inst : Synth_Instance_Acc;
+                         L : Int64;
+                         R : Memtyp;
+                         Loc : Node) return Memtyp
    is
       Lv : Memtyp;
    begin
@@ -1442,7 +1473,7 @@ package body Synth.Ieee.Numeric_Std is
          return Create_Memory (R.Typ); --  FIXME: typ
       end if;
       Lv := To_Signed (L, R.Typ);
-      return Mod_Sgn_Sgn (Lv, R, Loc);
+      return Mod_Sgn_Sgn (Inst, Lv, R, Loc);
    end Mod_Int_Sgn;
 
    function Minmax (L, R : Memtyp; Is_Signed : Boolean; Is_Max : Boolean)
diff --git a/src/synth/synth-ieee-numeric_std.ads b/src/synth/synth-ieee-numeric_std.ads
index 81158954c..26b8a4242 100644
--- a/src/synth/synth-ieee-numeric_std.ads
+++ b/src/synth/synth-ieee-numeric_std.ads
@@ -18,7 +18,10 @@
 
 with Types; use Types;
 
+with Vhdl.Nodes; use Vhdl.Nodes;
+
 with Elab.Vhdl_Objtypes; use Elab.Vhdl_Objtypes;
+with Elab.Vhdl_Context; use Elab.Vhdl_Context;
 
 with Synth.Ieee.Std_Logic_1164; use Synth.Ieee.Std_Logic_1164;
 
@@ -86,36 +89,65 @@ package Synth.Ieee.Numeric_Std is
                         return Memtyp;
 
    --  "/"
-   function Div_Uns_Uns (L, R : Memtyp; Loc : Location_Type) return Memtyp;
-   function Div_Uns_Nat (L : Memtyp; R : Uns64; Loc : Location_Type)
-                        return Memtyp;
-   function Div_Nat_Uns (L : Uns64; R : Memtyp; Loc : Location_Type)
-                        return Memtyp;
-   function Div_Sgn_Sgn (L, R : Memtyp; Loc : Location_Type) return Memtyp;
-   function Div_Sgn_Int (L : Memtyp; R : Int64; Loc : Location_Type)
-                        return Memtyp;
-   function Div_Int_Sgn (L : Int64; R : Memtyp; Loc : Location_Type)
-                        return Memtyp;
+   function Div_Uns_Uns (Inst : Synth_Instance_Acc;
+                         L, R : Memtyp;
+                         Loc : Node) return Memtyp;
+   function Div_Uns_Nat (Inst : Synth_Instance_Acc;
+                         L : Memtyp;
+                         R : Uns64;
+                         Loc : Node) return Memtyp;
+   function Div_Nat_Uns (Inst : Synth_Instance_Acc;
+                         L : Uns64;
+                         R : Memtyp;
+                         Loc : Node) return Memtyp;
+   function Div_Sgn_Sgn (Inst : Synth_Instance_Acc;
+                         L, R : Memtyp;
+                         Loc : Node) return Memtyp;
+   function Div_Sgn_Int (Inst : Synth_Instance_Acc;
+                         L : Memtyp;
+                         R : Int64;
+                         Loc : Node) return Memtyp;
+   function Div_Int_Sgn (Inst : Synth_Instance_Acc;
+                         L : Int64;
+                         R : Memtyp;
+                         Loc : Node) return Memtyp;
 
    --  "rem"
-   function Rem_Uns_Uns (L, R : Memtyp; Loc : Location_Type) return Memtyp;
-   function Rem_Uns_Nat (L : Memtyp; R : Uns64; Loc : Location_Type)
-                        return Memtyp;
-   function Rem_Nat_Uns (L : Uns64; R : Memtyp; Loc : Location_Type)
-                        return Memtyp;
-   function Rem_Sgn_Sgn (L, R : Memtyp; Loc : Location_Type) return Memtyp;
-   function Rem_Sgn_Int (L : Memtyp; R : Int64; Loc : Location_Type)
-                        return Memtyp;
-   function Rem_Int_Sgn (L : Int64; R : Memtyp; Loc : Location_Type)
-                        return Memtyp;
+   function Rem_Uns_Uns (Inst : Synth_Instance_Acc;
+                         L, R : Memtyp;
+                         Loc : Node) return Memtyp;
+   function Rem_Uns_Nat (Inst : Synth_Instance_Acc;
+                         L : Memtyp;
+                         R : Uns64;
+                         Loc : Node) return Memtyp;
+   function Rem_Nat_Uns (Inst : Synth_Instance_Acc;
+                         L : Uns64;
+                         R : Memtyp;
+                         Loc : Node) return Memtyp;
+   function Rem_Sgn_Sgn (Inst : Synth_Instance_Acc;
+                         L, R : Memtyp;
+                         Loc : Node) return Memtyp;
+   function Rem_Sgn_Int (Inst : Synth_Instance_Acc;
+                         L : Memtyp;
+                         R : Int64;
+                         Loc : Node) return Memtyp;
+   function Rem_Int_Sgn (Inst : Synth_Instance_Acc;
+                         L : Int64;
+                         R : Memtyp;
+                         Loc : Node) return Memtyp;
 
    --  "mod"
-   function Mod_Sgn_Sgn (L, R : Memtyp; Loc : Location_Type)
-                        return Memtyp;
-   function Mod_Sgn_Int (L : Memtyp; R : Int64; Loc : Location_Type)
-                        return Memtyp;
-   function Mod_Int_Sgn (L : Int64; R : Memtyp; Loc : Location_Type)
-                        return Memtyp;
+   function Mod_Sgn_Sgn (Inst : Synth_Instance_Acc;
+                         L, R : Memtyp;
+                         Loc : Node) return Memtyp;
+   function Mod_Sgn_Int (Inst : Synth_Instance_Acc;
+                         L : Memtyp;
+                         R : Int64;
+                         Loc : Node) return Memtyp;
+   function Mod_Int_Sgn (Inst : Synth_Instance_Acc;
+                         L : Int64;
+                         R : Memtyp;
+                         Loc : Node) return Memtyp;
 
    --  Shift
    function Shift_Vec (Val : Memtyp;
diff --git a/src/synth/synth-vhdl_aggr.adb b/src/synth/synth-vhdl_aggr.adb
index b8af2edf3..0df274872 100644
--- a/src/synth/synth-vhdl_aggr.adb
+++ b/src/synth/synth-vhdl_aggr.adb
@@ -23,7 +23,6 @@ with Netlists; use Netlists;
 with Netlists.Utils; use Netlists.Utils;
 with Netlists.Builders; use Netlists.Builders;
 
-with Vhdl.Errors; use Vhdl.Errors;
 with Vhdl.Utils; use Vhdl.Utils;
 
 with Elab.Memtype; use Elab.Memtype;
@@ -36,7 +35,8 @@ with Synth.Vhdl_Context; use Synth.Vhdl_Context;
 package body Synth.Vhdl_Aggr is
    type Stride_Array is array (Dim_Type range <>) of Nat32;
 
-   procedure Get_Index_Offset (Index : Int64;
+   procedure Get_Index_Offset (Syn_Inst : Synth_Instance_Acc;
+                               Index : Int64;
                                Bounds : Bound_Type;
                                Expr : Iir;
                                Off : out Uns32;
@@ -61,18 +61,20 @@ package body Synth.Vhdl_Aggr is
                return;
             end if;
       end case;
-      Error_Msg_Synth (+Expr, "index out of bounds");
+      Error_Msg_Synth (Syn_Inst, Expr, "index out of bounds");
       Off := 0;
       Err_P := True;
    end Get_Index_Offset;
 
-   procedure Get_Index_Offset (Index : Valtyp;
+   procedure Get_Index_Offset (Syn_Inst : Synth_Instance_Acc;
+                               Index : Valtyp;
                                Bounds : Bound_Type;
                                Expr : Iir;
                                Off : out Uns32;
                                Err_P : out Boolean) is
    begin
-      Get_Index_Offset (Read_Discrete (Index), Bounds, Expr, Off, Err_P);
+      Get_Index_Offset
+        (Syn_Inst, Read_Discrete (Index), Bounds, Expr, Off, Err_P);
    end Get_Index_Offset;
 
    function Fill_Stride (Typ : Type_Acc) return Stride_Array is
@@ -198,7 +200,7 @@ package body Synth.Vhdl_Aggr is
             pragma Assert (Stride = 1);
             if Bound.Len /= Width (Str_Len) then
                Error_Msg_Synth
-                 (+Aggr, "string length doesn't match bound length");
+                 (Syn_Inst, Aggr, "string length doesn't match bound length");
                Err_P := True;
             end if;
             for I in 1 .. Pos32'Min (Pos32 (Str_Len), Pos32 (Bound.Len)) loop
@@ -220,7 +222,8 @@ package body Synth.Vhdl_Aggr is
                when Iir_Kind_Choice_By_None =>
                   if Get_Element_Type_Flag (Assoc) then
                      if Pos >= First_Pos + Stride * Nat32 (Bound.Len) then
-                        Error_Msg_Synth (+Assoc, "element out of array bound");
+                        Error_Msg_Synth
+                          (Syn_Inst, Assoc, "element out of array bound");
                      else
                         Set_Elem (Pos);
                         Pos := Pos + Stride;
@@ -236,7 +239,7 @@ package body Synth.Vhdl_Aggr is
                         pragma Assert (Stride = 1);
                         if Pos - First_Pos > Nat32 (Bound.Len - Val_Len) then
                            Error_Msg_Synth
-                             (+Assoc, "element out of array bound");
+                             (Syn_Inst, Assoc, "element out of array bound");
                         else
                            Set_Vector (Pos, Nat32 (Val_Len), Val);
                            Pos := Pos + Nat32 (Val_Len);
@@ -267,9 +270,10 @@ package body Synth.Vhdl_Aggr is
                   begin
                      Idx := Synth_Expression (Syn_Inst, Ch);
                      if not Is_Static (Idx.Val) then
-                        Error_Msg_Synth (+Ch, "choice is not static");
+                        Error_Msg_Synth (Syn_Inst, Ch, "choice is not static");
                      else
-                        Get_Index_Offset (Idx, Bound, Ch, Off, Sub_Err);
+                        Get_Index_Offset
+                          (Syn_Inst, Idx, Bound, Ch, Off, Sub_Err);
                         Err_P := Err_P or Sub_Err;
                         exit when Err_P;
                         Set_Elem (First_Pos + Nat32 (Off) * Stride);
@@ -290,7 +294,8 @@ package body Synth.Vhdl_Aggr is
                            Get_Subtype_Object (Syn_Inst,
                                                Get_Base_Type (Get_Type (Ch))));
                         while In_Range (Rng, Read_Discrete (Val)) loop
-                           Get_Index_Offset (Val, Bound, Ch, Off, Sub_Err);
+                           Get_Index_Offset
+                             (Syn_Inst, Val, Bound, Ch, Off, Sub_Err);
                            Err_P := Err_P or Sub_Err;
                            exit when Err_P;
                            Set_Elem (First_Pos + Nat32 (Off) * Stride);
@@ -301,7 +306,8 @@ package body Synth.Vhdl_Aggr is
                         --  The direction must be the same.
                         if Rng.Dir /= Bound.Dir then
                            Error_Msg_Synth
-                             (+Assoc, "direction of range does not match "
+                             (Syn_Inst, Assoc,
+                              "direction of range does not match "
                                 & "direction of array");
                         end if;
                         --  FIXME: can the expression be unbounded ?
@@ -311,10 +317,11 @@ package body Synth.Vhdl_Aggr is
                         Rng_Len := Get_Range_Length (Rng);
                         if Get_Bound_Length (Val.Typ) /= Rng_Len then
                            Error_Msg_Synth
-                             (+Value, "length doesn't match range");
+                             (Syn_Inst, Value, "length doesn't match range");
                         end if;
                         pragma Assert (Stride = 1);
-                        Get_Index_Offset (Rng.Left, Bound, Ch, Off, Sub_Err);
+                        Get_Index_Offset
+                          (Syn_Inst, Rng.Left, Bound, Ch, Off, Sub_Err);
                         Err_P := Err_P or Sub_Err;
                         exit when Err_P;
                         Set_Vector
@@ -323,7 +330,7 @@ package body Synth.Vhdl_Aggr is
                   end;
                when others =>
                   Error_Msg_Synth
-                    (+Assoc, "unhandled association form");
+                    (Syn_Inst, Assoc, "unhandled association form");
             end case;
             Assoc := Get_Chain (Assoc);
             exit when Is_Null (Assoc);
@@ -333,7 +340,8 @@ package body Synth.Vhdl_Aggr is
       end loop;
 
       if not Err_P and then Nbr_Els /= Nat32 (Bound.Len) then
-         Error_Msg_Synth (+Aggr, "aggregate length doesn't match its bound");
+         Error_Msg_Synth
+           (Syn_Inst, Aggr, "aggregate length doesn't match its bound");
          Err_P := True;
       end if;
    end Fill_Array_Aggregate;
@@ -395,7 +403,7 @@ package body Synth.Vhdl_Aggr is
                   Set_Elem (Pos);
                when others =>
                   Error_Msg_Synth
-                    (+Assoc, "unhandled association form");
+                    (Syn_Inst, Assoc, "unhandled association form");
             end case;
             Assoc := Get_Chain (Assoc);
             exit when Is_Null (Assoc);
diff --git a/src/synth/synth-vhdl_decls.adb b/src/synth/synth-vhdl_decls.adb
index 091af79dd..c5611f014 100644
--- a/src/synth/synth-vhdl_decls.adb
+++ b/src/synth/synth-vhdl_decls.adb
@@ -206,7 +206,7 @@ package body Synth.Vhdl_Decls is
             else
                if not Is_Subprg then
                   Error_Msg_Synth
-                    (+Decl, "signals cannot be used in default value "
+                    (Syn_Inst, Decl, "signals cannot be used in default value "
                      & "of this constant");
                end if;
                Cst := Val;
@@ -435,7 +435,7 @@ package body Synth.Vhdl_Decls is
       if Obj_Typ.Kind = Type_Protected then
          if not Synth.Flags.Flag_Simulation then
             Error_Msg_Synth
-              (+Decl, "protected type variable is not synthesizable");
+              (Syn_Inst, Decl, "protected type variable is not synthesizable");
             Set_Error (Syn_Inst);
             Init := No_Valtyp;
          else
@@ -451,7 +451,7 @@ package body Synth.Vhdl_Decls is
         and then not Get_Instance_Const (Syn_Inst)
       then
          Error_Msg_Synth
-           (+Decl, "variable with access type is not synthesizable");
+           (Syn_Inst, Decl, "variable with access type is not synthesizable");
          --  FIXME: use a poison value ?
          Init := Create_Value_Default (Obj_Typ);
          Init := Unshare (Init, Instance_Pool);
@@ -465,7 +465,7 @@ package body Synth.Vhdl_Decls is
               and then not Is_Static (Init.Val)
             then
                Error_Msg_Synth
-                 (+Decl, "signals cannot be used in default value of "
+                 (Syn_Inst, Decl, "signals cannot be used in default value of "
                     & "this variable");
             end if;
          else
@@ -502,7 +502,7 @@ package body Synth.Vhdl_Decls is
    begin
       Init := Get_Value (Syn_Inst, Decl);
       if Init.Typ.Kind = Type_Protected then
-         Error_Msg_Synth (+Decl, "protected type not supported");
+         Error_Msg_Synth (Syn_Inst, Decl, "protected type not supported");
          Set_Error (Syn_Inst);
       else
          if Init.Val = null then
@@ -525,7 +525,8 @@ package body Synth.Vhdl_Decls is
       Val : Valtyp;
    begin
       if Get_Kind (Get_Parent (Decl)) = Iir_Kind_Package_Declaration then
-         Error_Msg_Synth (+Decl, "signals in packages are not supported");
+         Error_Msg_Synth
+           (Syn_Inst, Decl, "signals in packages are not supported");
          return;
       end if;
 
diff --git a/src/synth/synth-vhdl_environment.adb b/src/synth/synth-vhdl_environment.adb
index 7e726993c..ee3280824 100644
--- a/src/synth/synth-vhdl_environment.adb
+++ b/src/synth/synth-vhdl_environment.adb
@@ -205,8 +205,9 @@ package body Synth.Vhdl_Environment is
    procedure Error_Multiple_Assignments
      (Decl : Decl_Type; First_Off : Uns32; Last_Off : Uns32) is
    begin
-      Error_Msg_Synth (+Decl.Obj, "multiple assignments for %i offsets %v:%v",
-                       (+Decl.Obj, +First_Off, +Last_Off));
+      Error_Msg_Netlist
+        (+Decl.Obj, "multiple assignments for %i offsets %v:%v",
+         (+Decl.Obj, +First_Off, +Last_Off));
       Info_Subnet (Decl.Obj, Decl.Typ, First_Off, Last_Off + 1 - First_Off);
    end Error_Multiple_Assignments;
 
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb
index 1cb9f0ad1..f316f19e7 100644
--- a/src/synth/synth-vhdl_eval.adb
+++ b/src/synth/synth-vhdl_eval.adb
@@ -87,14 +87,15 @@ package body Synth.Vhdl_Eval is
       return Create_Vec_Type_By_Length (Prev.W, Prev.Arr_El);
    end Create_Res_Bound;
 
-   function Eval_Vector_Dyadic (Left, Right : Memtyp;
+   function Eval_Vector_Dyadic (Inst : Synth_Instance_Acc;
+                                Left, Right : Memtyp;
                                 Op : Table_2d;
                                 Loc : Syn_Src) return Memtyp
    is
       Res : Memtyp;
    begin
       if Left.Typ.W /= Right.Typ.W then
-         Error_Msg_Synth (+Loc, "length of operands mismatch");
+         Error_Msg_Synth (Inst, Loc, "length of operands mismatch");
          return Null_Memtyp;
       end if;
 
@@ -141,14 +142,15 @@ package body Synth.Vhdl_Eval is
       return Create_Memory_U8 (Std_Ulogic'Pos (Res), Left.Typ);
    end Eval_Logic_Scalar;
 
-   function Eval_Vector_Match (Left, Right : Memtyp;
+   function Eval_Vector_Match (Inst : Synth_Instance_Acc;
+                               Left, Right : Memtyp;
                                Neg : Boolean;
                                Loc : Syn_Src) return Memtyp
    is
       Res : Std_Ulogic;
    begin
       if Left.Typ.W /= Right.Typ.W then
-         Error_Msg_Synth (+Loc, "length of operands mismatch");
+         Error_Msg_Synth (Inst, Loc, "length of operands mismatch");
          return Null_Memtyp;
       end if;
 
@@ -168,7 +170,8 @@ package body Synth.Vhdl_Eval is
       return Create_Memory_U8 (Std_Ulogic'Pos (Res), Left.Typ.Arr_El);
    end Eval_Vector_Match;
 
-   function Eval_TF_Vector_Dyadic (Left, Right : Memtyp;
+   function Eval_TF_Vector_Dyadic (Inst : Synth_Instance_Acc;
+                                   Left, Right : Memtyp;
                                    Op : Tf_Table_2d;
                                    Loc : Syn_Src) return Memtyp
    is
@@ -176,7 +179,7 @@ package body Synth.Vhdl_Eval is
       L, R : Boolean;
    begin
       if Left.Typ.Sz /= Right.Typ.Sz then
-         Error_Msg_Synth (+Loc, "length mismatch");
+         Error_Msg_Synth (Inst, Loc, "length mismatch");
          return Null_Memtyp;
       end if;
 
@@ -389,14 +392,16 @@ package body Synth.Vhdl_Eval is
       return Res;
    end Execute_Shift_Operator;
 
-   procedure Check_Integer_Overflow
-     (Val : in out Int64; Typ : Type_Acc; Loc : Syn_Src) is
+   procedure Check_Integer_Overflow (Inst : Synth_Instance_Acc;
+                                     Val : in out Int64;
+                                     Typ : Type_Acc;
+                                     Loc : Syn_Src) is
    begin
       pragma Assert (Typ.Kind = Type_Discrete);
       case Typ.Sz is
          when 4 =>
             if Val < -2**31 or Val >= 2**31 then
-               Error_Msg_Synth (+Loc, "integer overflow");
+               Error_Msg_Synth (Inst, Loc, "integer overflow");
                --  Just keep the lower 32bit (and sign extend).
                Val := Int64
                  (To_Int32 (Uns32 (To_Uns64 (Val) and 16#ffff_ffff#)));
@@ -413,7 +418,8 @@ package body Synth.Vhdl_Eval is
       return Create_Memory_U8 (Boolean'Pos (V), Boolean_Type);
    end Create_Memory_Boolean;
 
-   function Eval_Static_Dyadic_Predefined (Imp : Node;
+   function Eval_Static_Dyadic_Predefined (Inst : Synth_Instance_Acc;
+                                           Imp : Node;
                                            Res_Typ : Type_Acc;
                                            Left : Memtyp;
                                            Right : Memtyp;
@@ -439,7 +445,7 @@ package body Synth.Vhdl_Eval is
                Res : Int64;
             begin
                Res := Read_Discrete (Left) + Read_Discrete (Right);
-               Check_Integer_Overflow (Res, Res_Typ, Expr);
+               Check_Integer_Overflow (Inst, Res, Res_Typ, Expr);
                return Create_Memory_Discrete (Res, Res_Typ);
             end;
          when Iir_Predefined_Integer_Minus
@@ -448,7 +454,7 @@ package body Synth.Vhdl_Eval is
                Res : Int64;
             begin
                Res := Read_Discrete (Left) - Read_Discrete (Right);
-               Check_Integer_Overflow (Res, Res_Typ, Expr);
+               Check_Integer_Overflow (Inst, Res, Res_Typ, Expr);
                return Create_Memory_Discrete (Res, Res_Typ);
             end;
          when Iir_Predefined_Integer_Mul
@@ -458,7 +464,7 @@ package body Synth.Vhdl_Eval is
                Res : Int64;
             begin
                Res := Read_Discrete (Left) * Read_Discrete (Right);
-               Check_Integer_Overflow (Res, Res_Typ, Expr);
+               Check_Integer_Overflow (Inst, Res, Res_Typ, Expr);
                return Create_Memory_Discrete (Res, Res_Typ);
             end;
          when Iir_Predefined_Integer_Div
@@ -468,7 +474,7 @@ package body Synth.Vhdl_Eval is
                Res : Int64;
             begin
                Res := Read_Discrete (Left) / Read_Discrete (Right);
-               Check_Integer_Overflow (Res, Res_Typ, Expr);
+               Check_Integer_Overflow (Inst, Res, Res_Typ, Expr);
                return Create_Memory_Discrete (Res, Res_Typ);
             end;
          when Iir_Predefined_Integer_Mod =>
@@ -476,7 +482,7 @@ package body Synth.Vhdl_Eval is
                Res : Int64;
             begin
                Res := Read_Discrete (Left) mod Read_Discrete (Right);
-               Check_Integer_Overflow (Res, Res_Typ, Expr);
+               Check_Integer_Overflow (Inst, Res, Res_Typ, Expr);
                return Create_Memory_Discrete (Res, Res_Typ);
             end;
          when Iir_Predefined_Integer_Rem =>
@@ -484,7 +490,7 @@ package body Synth.Vhdl_Eval is
                Res : Int64;
             begin
                Res := Read_Discrete (Left) rem Read_Discrete (Right);
-               Check_Integer_Overflow (Res, Res_Typ, Expr);
+               Check_Integer_Overflow (Inst, Res, Res_Typ, Expr);
                return Create_Memory_Discrete (Res, Res_Typ);
             end;
 
@@ -499,7 +505,7 @@ package body Synth.Vhdl_Eval is
                Rv := Std_Integer (Read_Discrete (Right));
                Grt.Arith.Exp_I64 (Lv, Rv, Res, Ovf);
                if Ovf then
-                  Error_Msg_Synth (+Expr, "exponentiation overflow");
+                  Error_Msg_Synth (Inst, Expr, "exponentiation overflow");
                   Res := 0;
                end if;
                return Create_Memory_Discrete (Int64 (Res), Res_Typ);
@@ -775,17 +781,17 @@ package body Synth.Vhdl_Eval is
               (Left, Read_Discrete (Right), 0, Def);
 
          when Iir_Predefined_TF_Array_And =>
-            return Eval_TF_Vector_Dyadic (Left, Right, Tf_2d_And, Expr);
+            return Eval_TF_Vector_Dyadic (Inst, Left, Right, Tf_2d_And, Expr);
          when Iir_Predefined_TF_Array_Or =>
-            return Eval_TF_Vector_Dyadic (Left, Right, Tf_2d_Or, Expr);
+            return Eval_TF_Vector_Dyadic (Inst, Left, Right, Tf_2d_Or, Expr);
          when Iir_Predefined_TF_Array_Xor =>
-            return Eval_TF_Vector_Dyadic (Left, Right, Tf_2d_Xor, Expr);
+            return Eval_TF_Vector_Dyadic (Inst, Left, Right, Tf_2d_Xor, Expr);
          when Iir_Predefined_TF_Array_Nand =>
-            return Eval_TF_Vector_Dyadic (Left, Right, Tf_2d_Nand, Expr);
+            return Eval_TF_Vector_Dyadic (Inst, Left, Right, Tf_2d_Nand, Expr);
          when Iir_Predefined_TF_Array_Nor =>
-            return Eval_TF_Vector_Dyadic (Left, Right, Tf_2d_Nor, Expr);
+            return Eval_TF_Vector_Dyadic (Inst, Left, Right, Tf_2d_Nor, Expr);
          when Iir_Predefined_TF_Array_Xnor =>
-            return Eval_TF_Vector_Dyadic (Left, Right, Tf_2d_Xnor, Expr);
+            return Eval_TF_Vector_Dyadic (Inst, Left, Right, Tf_2d_Xnor, Expr);
 
          when Iir_Predefined_TF_Element_Array_Or =>
             return Eval_TF_Array_Element (Left, Right, Tf_2d_Or);
@@ -820,32 +826,32 @@ package body Synth.Vhdl_Eval is
          when Iir_Predefined_Ieee_1164_Vector_And
            | Iir_Predefined_Ieee_Numeric_Std_And_Uns_Uns
            | Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Sgn =>
-            return Eval_Vector_Dyadic (Left, Right, And_Table, Expr);
+            return Eval_Vector_Dyadic (Inst, Left, Right, And_Table, Expr);
 
          when Iir_Predefined_Ieee_1164_Vector_Nand
            | Iir_Predefined_Ieee_Numeric_Std_Nand_Uns_Uns
            | Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn_Sgn =>
-            return Eval_Vector_Dyadic (Left, Right, Nand_Table, Expr);
+            return Eval_Vector_Dyadic (Inst, Left, Right, Nand_Table, Expr);
 
          when Iir_Predefined_Ieee_1164_Vector_Or
            | Iir_Predefined_Ieee_Numeric_Std_Or_Uns_Uns
            | Iir_Predefined_Ieee_Numeric_Std_Or_Sgn_Sgn =>
-            return Eval_Vector_Dyadic (Left, Right, Or_Table, Expr);
+            return Eval_Vector_Dyadic (Inst, Left, Right, Or_Table, Expr);
 
          when Iir_Predefined_Ieee_1164_Vector_Nor
            | Iir_Predefined_Ieee_Numeric_Std_Nor_Uns_Uns
            | Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn_Sgn =>
-            return Eval_Vector_Dyadic (Left, Right, Nor_Table, Expr);
+            return Eval_Vector_Dyadic (Inst, Left, Right, Nor_Table, Expr);
 
          when Iir_Predefined_Ieee_1164_Vector_Xor
            | Iir_Predefined_Ieee_Numeric_Std_Xor_Uns_Uns
            | Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn_Sgn =>
-            return Eval_Vector_Dyadic (Left, Right, Xor_Table, Expr);
+            return Eval_Vector_Dyadic (Inst, Left, Right, Xor_Table, Expr);
 
          when Iir_Predefined_Ieee_1164_Vector_Xnor
             | Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns_Uns
             | Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn_Sgn =>
-            return Eval_Vector_Dyadic (Left, Right, Xnor_Table, Expr);
+            return Eval_Vector_Dyadic (Inst, Left, Right, Xnor_Table, Expr);
 
          when Iir_Predefined_Ieee_1164_Scalar_And =>
             return Eval_Logic_Scalar (Left, Right, And_Table);
@@ -874,9 +880,9 @@ package body Synth.Vhdl_Eval is
             return Eval_Logic_Scalar (Left, Right, Match_Lt_Table);
 
          when Iir_Predefined_Std_Ulogic_Array_Match_Equality =>
-            return Eval_Vector_Match (Left, Right, False, Expr);
+            return Eval_Vector_Match (Inst, Left, Right, False, Expr);
          when Iir_Predefined_Std_Ulogic_Array_Match_Inequality =>
-            return Eval_Vector_Match (Left, Right, True, Expr);
+            return Eval_Vector_Match (Inst, Left, Right, True, Expr);
 
          when Iir_Predefined_Ieee_1164_And_Suv_Log
             | Iir_Predefined_Ieee_Numeric_Std_And_Uns_Log
@@ -1651,42 +1657,46 @@ package body Synth.Vhdl_Eval is
             return Mul_Sgn_Uns_Sgn (Left, Right, +Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Div_Uns_Uns =>
-            return Div_Uns_Uns (Left, Right, +Expr);
+            return Div_Uns_Uns (Inst, Left, Right, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Div_Uns_Nat =>
-            return Div_Uns_Nat (Left, To_Uns64 (Read_Discrete (Right)), +Expr);
+            return Div_Uns_Nat
+              (Inst, Left, To_Uns64 (Read_Discrete (Right)), Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Div_Nat_Uns =>
-            return Div_Nat_Uns (To_Uns64 (Read_Discrete (Left)), Right, +Expr);
+            return Div_Nat_Uns
+              (Inst, To_Uns64 (Read_Discrete (Left)), Right, Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Div_Sgn_Sgn =>
-            return Div_Sgn_Sgn (Left, Right, +Expr);
+            return Div_Sgn_Sgn (Inst, Left, Right, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Div_Int_Sgn =>
-            return Div_Int_Sgn (Read_Discrete (Left), Right, +Expr);
+            return Div_Int_Sgn (Inst, Read_Discrete (Left), Right, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Div_Sgn_Int =>
-            return Div_Sgn_Int (Left, Read_Discrete (Right), +Expr);
+            return Div_Sgn_Int (Inst, Left, Read_Discrete (Right), Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Rem_Uns_Uns
             | Iir_Predefined_Ieee_Numeric_Std_Mod_Uns_Uns =>
-            return Rem_Uns_Uns (Left, Right, +Expr);
+            return Rem_Uns_Uns (Inst, Left, Right, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Rem_Uns_Nat
             | Iir_Predefined_Ieee_Numeric_Std_Mod_Uns_Nat =>
-            return Rem_Uns_Nat (Left, To_Uns64 (Read_Discrete (Right)), +Expr);
+            return Rem_Uns_Nat
+              (Inst, Left, To_Uns64 (Read_Discrete (Right)), Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Rem_Nat_Uns
             | Iir_Predefined_Ieee_Numeric_Std_Mod_Nat_Uns =>
-            return Rem_Nat_Uns (To_Uns64 (Read_Discrete (Left)), Right, +Expr);
+            return Rem_Nat_Uns
+              (Inst, To_Uns64 (Read_Discrete (Left)), Right, Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Rem_Sgn_Sgn =>
-            return Rem_Sgn_Sgn (Left, Right, +Expr);
+            return Rem_Sgn_Sgn (Inst, Left, Right, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Rem_Int_Sgn =>
-            return Rem_Int_Sgn (Read_Discrete (Left), Right, +Expr);
+            return Rem_Int_Sgn (Inst, Read_Discrete (Left), Right, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Rem_Sgn_Int =>
-            return Rem_Sgn_Int (Left, Read_Discrete (Right), +Expr);
+            return Rem_Sgn_Int (Inst, Left, Read_Discrete (Right), Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Mod_Sgn_Sgn =>
-            return Mod_Sgn_Sgn (Left, Right, +Expr);
+            return Mod_Sgn_Sgn (Inst, Left, Right, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Mod_Int_Sgn =>
-            return Mod_Int_Sgn (Read_Discrete (Left), Right, +Expr);
+            return Mod_Int_Sgn (Inst, Read_Discrete (Left), Right, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Mod_Sgn_Int =>
-            return Mod_Sgn_Int (Left, Read_Discrete (Right), +Expr);
+            return Mod_Sgn_Int (Inst, Left, Read_Discrete (Right), Expr);
 
          when Iir_Predefined_Ieee_Numeric_Std_Srl_Uns_Int
            |  Iir_Predefined_Ieee_Numeric_Std_Srl_Sgn_Int =>
@@ -1785,7 +1795,7 @@ package body Synth.Vhdl_Eval is
 
          when others =>
             Error_Msg_Synth
-              (+Expr, "eval_static_dyadic_predefined: unhandled "
+              (Inst, Expr, "eval_static_dyadic_predefined: unhandled "
                  & Iir_Predefined_Functions'Image (Def));
             return Null_Memtyp;
       end case;
@@ -1978,9 +1988,10 @@ package body Synth.Vhdl_Eval is
       end case;
    end Eval_Vector_Minimum;
 
-   function Eval_Static_Monadic_Predefined (Imp : Node;
-                                             Operand : Memtyp;
-                                             Expr : Node) return Memtyp
+   function Eval_Static_Monadic_Predefined (Inst : Synth_Instance_Acc;
+                                            Imp : Node;
+                                            Operand : Memtyp;
+                                            Expr : Node) return Memtyp
    is
       Def : constant Iir_Predefined_Functions :=
         Get_Implicit_Definition (Imp);
@@ -2106,7 +2117,7 @@ package body Synth.Vhdl_Eval is
 
          when others =>
             Error_Msg_Synth
-              (+Expr, "eval_static_monadic_predefined: unhandled "
+              (Inst, Expr, "eval_static_monadic_predefined: unhandled "
                  & Iir_Predefined_Functions'Image (Def));
             raise Internal_Error;
       end case;
@@ -2396,7 +2407,8 @@ package body Synth.Vhdl_Eval is
       return Res;
    end Eval_To_X01;
 
-   function Eval_Static_Predefined_Function_Call (Param1 : Valtyp;
+   function Eval_Static_Predefined_Function_Call (Inst : Synth_Instance_Acc;
+                                                  Param1 : Valtyp;
                                                   Param2 : Valtyp;
                                                   Res_Typ : Type_Acc;
                                                   Expr : Node) return Memtyp
@@ -2525,7 +2537,7 @@ package body Synth.Vhdl_Eval is
                end loop;
                if Unit = Null_Iir then
                   Error_Msg_Synth
-                    (+Expr, "to_string for time called with wrong unit");
+                    (Inst, Expr, "to_string for time called with wrong unit");
                end if;
                Grt.To_Strings.To_String (Str, First,
                                          Ghdl_I64 (Read_Discrete (Param1)),
@@ -2958,7 +2970,7 @@ package body Synth.Vhdl_Eval is
          when others =>
             null;
       end case;
-      Error_Msg_Synth (+Expr, "unhandled (static) function: "
+      Error_Msg_Synth (Inst, Expr, "unhandled (static) function: "
                          & Iir_Predefined_Functions'Image (Def));
       return Null_Memtyp;
    end Eval_Static_Predefined_Function_Call;
diff --git a/src/synth/synth-vhdl_eval.ads b/src/synth/synth-vhdl_eval.ads
index 2b689d89a..f1482de5f 100644
--- a/src/synth/synth-vhdl_eval.ads
+++ b/src/synth/synth-vhdl_eval.ads
@@ -18,20 +18,26 @@
 
 with Elab.Vhdl_Objtypes; use Elab.Vhdl_Objtypes;
 with Elab.Vhdl_Values; use Elab.Vhdl_Values;
+with Elab.Vhdl_Context; use Elab.Vhdl_Context;
 
 with Vhdl.Nodes; use Vhdl.Nodes;
 
 package Synth.Vhdl_Eval is
-   function Eval_Static_Dyadic_Predefined (Imp : Node;
+   --  Note: INST is only used to report errors.
+
+   function Eval_Static_Dyadic_Predefined (Inst : Synth_Instance_Acc;
+                                           Imp : Node;
                                            Res_Typ : Type_Acc;
                                            Left : Memtyp;
                                            Right : Memtyp;
                                            Expr : Node) return Memtyp;
-   function Eval_Static_Monadic_Predefined (Imp : Node;
+   function Eval_Static_Monadic_Predefined (Inst : Synth_Instance_Acc;
+                                            Imp : Node;
                                             Operand : Memtyp;
                                             Expr : Node) return Memtyp;
 
-   function Eval_Static_Predefined_Function_Call (Param1 : Valtyp;
+   function Eval_Static_Predefined_Function_Call (Inst : Synth_Instance_Acc;
+                                                  Param1 : Valtyp;
                                                   Param2 : Valtyp;
                                                   Res_Typ : Type_Acc;
                                                   Expr : Node) return Memtyp;
diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb
index d0e6a6115..613f0406c 100644
--- a/src/synth/synth-vhdl_expr.adb
+++ b/src/synth/synth-vhdl_expr.adb
@@ -41,7 +41,6 @@ with Elab.Vhdl_Annotations;
 with Elab.Vhdl_Heap; use Elab.Vhdl_Heap;
 with Elab.Vhdl_Types; use Elab.Vhdl_Types;
 with Elab.Vhdl_Expr;
-with Elab.Debugger;
 
 with Synth.Errors; use Synth.Errors;
 with Synth.Vhdl_Environment;
@@ -581,8 +580,7 @@ package body Synth.Vhdl_Expr is
                      Val : constant Int64 := Read_Discrete (Vt);
                   begin
                      if not In_Range (Dtype.Drange, Val) then
-                        Error_Msg_Synth (+Loc, "value out of range");
-                        Elab.Debugger.Debug_Error (Syn_Inst, Loc);
+                        Error_Msg_Synth (Syn_Inst, Loc, "value out of range");
                         return No_Valtyp;
                      end if;
                      return Create_Value_Discrete (Val, Dtype);
@@ -598,9 +596,9 @@ package body Synth.Vhdl_Expr is
             pragma Assert (Vtype.Kind = Type_Vector
                              or Vtype.Kind = Type_Slice);
             if Dtype.W /= Vtype.W then
-               Error_Msg_Synth
-                 (+Loc, "mismatching vector length; got %v, expect %v",
-                  (Errorout."+" (Vtype.W), +Dtype.W));
+               Error_Msg_Synth (Syn_Inst, Loc,
+                                "mismatching vector length; got %v, expect %v",
+                                (+Vtype.W, +Dtype.W));
                return No_Valtyp;
             end if;
             if Bounds then
@@ -622,7 +620,8 @@ package body Synth.Vhdl_Expr is
                loop
                   pragma Assert (Src_Typ.Alast = Dst_Typ.Alast);
                   if Src_Typ.Abound.Len /= Dst_Typ.Abound.Len then
-                     Error_Msg_Synth (+Loc, "mismatching array bounds");
+                     Error_Msg_Synth
+                       (Syn_Inst, Loc, "mismatching array bounds");
                      return No_Valtyp;
                   end if;
                   exit when Src_Typ.Alast;
@@ -719,8 +718,7 @@ package body Synth.Vhdl_Expr is
 
    procedure Bound_Error (Syn_Inst : Synth_Instance_Acc; Loc : Node) is
    begin
-      Error_Msg_Synth (+Loc, "index not within bounds");
-      Elab.Debugger.Debug_Error (Syn_Inst, Loc);
+      Error_Msg_Synth (Syn_Inst, Loc, "index not within bounds");
    end Bound_Error;
 
    --  Convert index IDX in PFX to an offset.
@@ -962,7 +960,8 @@ package body Synth.Vhdl_Expr is
 
    --  Identify LEFT to/downto RIGHT as:
    --  INP * STEP + WIDTH - 1 + OFF to/downto INP * STEP + OFF
-   procedure Synth_Extract_Dyn_Suffix (Ctxt : Context_Acc;
+   procedure Synth_Extract_Dyn_Suffix (Syn_Inst : Synth_Instance_Acc;
+                                       Ctxt : Context_Acc;
                                        Loc : Node;
                                        Pfx_Bnd : Bound_Type;
                                        Left : Net;
@@ -999,14 +998,16 @@ package body Synth.Vhdl_Expr is
 
       if not Same_Net (L_Inp, R_Inp) then
          Error_Msg_Synth
-           (+Loc, "cannot extract same variable part for dynamic slice");
+           (Syn_Inst, Loc,
+            "cannot extract same variable part for dynamic slice");
          return;
       end if;
       Inp := L_Inp;
 
       if L_Fac /= R_Fac then
          Error_Msg_Synth
-           (+Loc, "cannot extract same constant factor for dynamic slice");
+           (Syn_Inst, Loc,
+            "cannot extract same constant factor for dynamic slice");
          return;
       end if;
 
@@ -1121,7 +1122,7 @@ package body Synth.Vhdl_Expr is
       Len : Uns32;
    begin
       if Pfx_Bnd.Dir /= Dir then
-         Error_Msg_Synth (+Name, "direction mismatch in slice");
+         Error_Msg_Synth (Syn_Inst, Name, "direction mismatch in slice");
          Off := (0, 0);
          if Dir = Dir_To then
             Res_Bnd := (Dir => Dir_To, Left => 1, Right => 0, Len => 0);
@@ -1145,8 +1146,7 @@ package body Synth.Vhdl_Expr is
          if not In_Bounds (Pfx_Bnd, Int32 (L))
            or else not In_Bounds (Pfx_Bnd, Int32 (R))
          then
-            Error_Msg_Synth (+Name, "index not within bounds");
-            Elab.Debugger.Debug_Error (Syn_Inst, Expr);
+            Error_Msg_Synth (Syn_Inst, Expr, "index not within bounds");
             Off := (0, 0);
             return;
          end if;
@@ -1211,7 +1211,7 @@ package body Synth.Vhdl_Expr is
             end;
          when others =>
             Error_Msg_Synth
-              (+Expr, "only range expression supported for slices");
+              (Syn_Inst, Expr, "only range expression supported for slices");
             Res_Bnd := (Dir => Dir_To, Left => 1, Right => 0, Len => 0);
             return;
       end case;
@@ -1225,7 +1225,7 @@ package body Synth.Vhdl_Expr is
                                    El_Typ, Res_Bnd, Off);
       else
          if Pfx_Bnd.Dir /= Dir then
-            Error_Msg_Synth (+Name, "direction mismatch in slice");
+            Error_Msg_Synth (Syn_Inst, Name, "direction mismatch in slice");
             if Dir = Dir_To then
                Res_Bnd := (Dir => Dir_To, Left => 1, Right => 0, Len => 0);
             else
@@ -1236,14 +1236,14 @@ package body Synth.Vhdl_Expr is
 
          if Is_Static (Left.Val) or else Is_Static (Right.Val) then
             Error_Msg_Synth
-              (+Name, "left and right bounds of a slice must be "
+              (Syn_Inst, Name, "left and right bounds of a slice must be "
                  & "either constant or dynamic");
             return;
          end if;
 
-         Synth_Extract_Dyn_Suffix
-           (Ctxt, Name, Pfx_Bnd, Get_Net (Ctxt, Left), Get_Net (Ctxt, Right),
-            Inp, Step, Off.Net_Off, Res_Bnd.Len);
+         Synth_Extract_Dyn_Suffix (Syn_Inst, Ctxt, Name, Pfx_Bnd,
+                                   Get_Net (Ctxt, Left), Get_Net (Ctxt, Right),
+                                   Inp, Step, Off.Net_Off, Res_Bnd.Len);
          if Inp = No_Net then
             return;
          end if;
@@ -1310,14 +1310,16 @@ package body Synth.Vhdl_Expr is
    begin
       Clk := Get_Net (Ctxt, Synth_Expression (Syn_Inst, Prefix));
       if Get_Kind (Expr) /= Iir_Kind_Equality_Operator then
-         Error_Msg_Synth (+Expr, "ill-formed clock-level, '=' expected");
+         Error_Msg_Synth
+           (Syn_Inst, Expr, "ill-formed clock-level, '=' expected");
          Res := Build_Posedge (Ctxt, Clk);
          Set_Location (Res, Expr);
          return Res;
       end if;
       Imp := Get_Implementation (Expr);
       if Get_Implicit_Definition (Imp) /= Iir_Predefined_Enum_Equality then
-         Error_Msg_Synth (+Expr, "ill-formed clock-level, '=' expected");
+         Error_Msg_Synth
+           (Syn_Inst, Expr, "ill-formed clock-level, '=' expected");
          Res := Build_Posedge (Ctxt, Clk);
          Set_Location (Res, Expr);
          return Res;
@@ -1325,14 +1327,14 @@ package body Synth.Vhdl_Expr is
 
       Left := Get_Left (Expr);
       if not Is_Same_Clock (Syn_Inst, Prefix, Left, Clk) then
-         Error_Msg_Synth (+Left, "clock signal name doesn't match");
+         Error_Msg_Synth (Syn_Inst, Left, "clock signal name doesn't match");
       end if;
 
       Right := Get_Right (Expr);
       Lit_Type := Get_Base_Type (Get_Type (Right));
       Lit := Synth_Expression (Syn_Inst, Right);
       if Lit.Val.Kind /= Value_Memory then
-         Error_Msg_Synth (+Right, "clock-level is not a constant");
+         Error_Msg_Synth (Syn_Inst, Right, "clock-level is not a constant");
          Posedge := True;
       else
          if Lit_Type = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Type then
@@ -1343,7 +1345,7 @@ package body Synth.Vhdl_Expr is
                   Posedge := True;
                when others =>
                   Error_Msg_Synth
-                    (+Right, "clock-level must be either '0' or '1'");
+                    (Syn_Inst, Right, "clock-level must be either '0' or '1'");
                   Posedge := True;
             end case;
          else
@@ -1415,14 +1417,14 @@ package body Synth.Vhdl_Expr is
                           or V > Fp64 (Conv_Typ.Drange.Left);
                   end case;
                   if Err then
-                     Error_Msg_Synth (+Loc, "value out of range");
-                     Elab.Debugger.Debug_Error (Syn_Inst, Loc);
+                     Error_Msg_Synth (Syn_Inst, Loc, "value out of range");
                      return No_Valtyp;
                   end if;
                   return Create_Value_Discrete (Int64 (V), Conv_Typ);
                end;
             else
-               Error_Msg_Synth (+Loc, "unhandled type conversion (to int)");
+               Error_Msg_Synth (Syn_Inst, Loc,
+                                "unhandled type conversion (to int)");
                return No_Valtyp;
             end if;
          when Type_Float =>
@@ -1430,7 +1432,8 @@ package body Synth.Vhdl_Expr is
                return Create_Value_Float
                  (Fp64 (Read_Discrete (Val)), Conv_Typ);
             else
-               Error_Msg_Synth (+Loc, "unhandled type conversion (to float)");
+               Error_Msg_Synth (Syn_Inst, Loc,
+                                "unhandled type conversion (to float)");
                return No_Valtyp;
             end if;
          when Type_Vector
@@ -1443,7 +1446,7 @@ package body Synth.Vhdl_Expr is
            | Type_Logic =>
             return Val;
          when others =>
-            Error_Msg_Synth (+Loc, "unhandled type conversion");
+            Error_Msg_Synth (Syn_Inst, Loc, "unhandled type conversion");
             return No_Valtyp;
       end case;
    end Synth_Type_Conversion;
@@ -1464,7 +1467,8 @@ package body Synth.Vhdl_Expr is
       return Synth_Type_Conversion (Syn_Inst, Val, Conv_Typ, Conv);
    end Synth_Type_Conversion;
 
-   function Error_Ieee_Operator (Imp : Node; Loc : Node) return Boolean
+   function Error_Ieee_Operator
+     (Syn_Inst : Synth_Instance_Acc; Imp : Node; Loc : Node) return Boolean
    is
       use Std_Names;
       Parent : constant Iir := Get_Parent (Imp);
@@ -1483,10 +1487,10 @@ package body Synth.Vhdl_Expr is
                | Name_Numeric_Std
                | Name_Numeric_Bit
                | Name_Math_Real =>
-               Error_Msg_Synth
-                 (+Loc, "unhandled predefined IEEE operator %i", +Imp);
-               Error_Msg_Synth
-                 (+Imp, " declared here");
+               Error_Msg_Synth (Syn_Inst, Loc,
+                                "unhandled predefined IEEE operator %i", +Imp);
+               Error_Msg_Synth (Syn_Inst, Imp,
+                                " declared here");
                return True;
             when others =>
                --  ieee 2008 packages are handled like regular packages.
@@ -1547,8 +1551,7 @@ package body Synth.Vhdl_Expr is
                   end if;
             end case;
             if Err then
-               Error_Msg_Synth (+Expr, "value out of range");
-               Elab.Debugger.Debug_Error (Syn_Inst, Expr);
+               Error_Msg_Synth (Syn_Inst, Expr, "value out of range");
                return No_Valtyp;
             end if;
             Res := Create_Value_Memory (Dtype, Expr_Pool'Access);
@@ -1978,7 +1981,7 @@ package body Synth.Vhdl_Expr is
                        (Syn_Inst, Id_Or, Get_Left (Expr), Get_Right (Expr),
                         Bit_Type, Expr);
                   when Iir_Predefined_None =>
-                     if Error_Ieee_Operator (Imp, Expr) then
+                     if Error_Ieee_Operator (Syn_Inst, Imp, Expr) then
                         return No_Valtyp;
                      else
                         return Synth_User_Operator
@@ -1997,7 +2000,7 @@ package body Synth.Vhdl_Expr is
                  Get_Implicit_Definition (Imp);
             begin
                if Def = Iir_Predefined_None then
-                  if Error_Ieee_Operator (Imp, Expr) then
+                  if Error_Ieee_Operator (Syn_Inst, Imp, Expr) then
                      return No_Valtyp;
                   else
                      return Synth_User_Operator
@@ -2030,7 +2033,8 @@ package body Synth.Vhdl_Expr is
                         return Hook_Signal_Expr (Res);
                      end if;
                      Error_Msg_Synth
-                       (+Expr, "cannot use signal value during elaboration");
+                       (Syn_Inst, Expr,
+                        "cannot use signal value during elaboration");
                      return No_Valtyp;
                   elsif (Res.Val.Kind = Value_Quantity
                            or else
@@ -2040,7 +2044,8 @@ package body Synth.Vhdl_Expr is
                      if Hook_Quantity_Expr /= null then
                         return Hook_Quantity_Expr (Res);
                      end if;
-                     Error_Msg_Synth (+Expr, "cannot use quantity value");
+                     Error_Msg_Synth
+                       (Syn_Inst, Expr, "cannot use quantity value");
                      return No_Valtyp;
                   end if;
                end if;
@@ -2333,7 +2338,7 @@ package body Synth.Vhdl_Expr is
                return Create_Value_Access (Acc, Expr_Type);
             end;
          when Iir_Kind_Stable_Attribute =>
-            Error_Msg_Synth (+Expr, "signal attribute not supported");
+            Error_Msg_Synth (Syn_Inst, Expr, "signal attribute not supported");
             return No_Valtyp;
          when Iir_Kind_Psl_Prev =>
             return Synth_Psl_Prev (Syn_Inst, Expr);
@@ -2348,26 +2353,25 @@ package body Synth.Vhdl_Expr is
          when Iir_Kind_Psl_Onehot0 =>
             return Synth_Psl_Onehot0(Syn_Inst, Expr);
          when Iir_Kind_Overflow_Literal =>
-            Error_Msg_Synth (+Expr, "out of bound expression");
-            Elab.Debugger.Debug_Error (Syn_Inst, Expr);
+            Error_Msg_Synth (Syn_Inst, Expr, "out of bound expression");
             return No_Valtyp;
          when Iir_Kind_Event_Attribute =>
             if Hook_Event_Attribute /= null then
                return Hook_Event_Attribute (Syn_Inst, Expr);
             end if;
-            Error_Msg_Synth (+Expr, "event attribute not allowed");
+            Error_Msg_Synth (Syn_Inst, Expr, "event attribute not allowed");
             return No_Valtyp;
          when Iir_Kind_Active_Attribute =>
             if Hook_Active_Attribute /= null then
                return Hook_Active_Attribute (Syn_Inst, Expr);
             end if;
-            Error_Msg_Synth (+Expr, "active attribute not allowed");
+            Error_Msg_Synth (Syn_Inst, Expr, "active attribute not allowed");
             return No_Valtyp;
          when Iir_Kind_Dot_Attribute =>
             if Hook_Dot_Attribute /= null then
                return Hook_Dot_Attribute (Syn_Inst, Expr);
             end if;
-            Error_Msg_Synth (+Expr, "dot attribute not allowed");
+            Error_Msg_Synth (Syn_Inst, Expr, "dot attribute not allowed");
             return No_Valtyp;
          when others =>
             Error_Kind ("synth_expression_with_type", Expr);
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb
index 2996ea0dd..1bbfbb133 100644
--- a/src/synth/synth-vhdl_oper.adb
+++ b/src/synth/synth-vhdl_oper.adb
@@ -584,7 +584,8 @@ package body Synth.Vhdl_Oper is
          N : Net;
       begin
          if Left.Typ.W /= Right.Typ.W then
-            Error_Msg_Synth (+Expr, "operands don't have the same length");
+            Error_Msg_Synth
+              (Syn_Inst, Expr, "operands don't have the same length");
             return No_Valtyp;
          end if;
          N := Build_Dyadic (Ctxt, Id,
@@ -709,7 +710,8 @@ package body Synth.Vhdl_Oper is
                   R1 := Build2_Trunc (Ctxt, Id_Utrunc, R1, Ww, +Expr);
                else
                   Error_Msg_Synth
-                    (+Expr, "vector length of rotation must be a power of 2");
+                    (Syn_Inst, Expr,
+                     "vector length of rotation must be a power of 2");
                   return Left;
                end if;
             end if;
@@ -734,7 +736,7 @@ package body Synth.Vhdl_Oper is
 
       if Is_Static_Val (Left.Val) and Is_Static_Val (Right.Val) then
          Srec := Eval_Static_Dyadic_Predefined
-           (Imp, Expr_Typ,
+           (Syn_Inst, Imp, Expr_Typ,
             Get_Value_Memtyp (Left), Get_Value_Memtyp (Right), Expr);
          if Srec = Null_Memtyp then
             return No_Valtyp;
@@ -882,7 +884,8 @@ package body Synth.Vhdl_Oper is
             begin
                if Left.Typ.W /= Right.Typ.W then
                   Error_Msg_Synth
-                    (+Expr, "operands of ?= don't have the same size");
+                    (Syn_Inst, Expr,
+                     "operands of ?= don't have the same size");
                   return Create_Value_Discrete (0, Bit_Type);
                end if;
 
@@ -910,8 +913,8 @@ package body Synth.Vhdl_Oper is
                Res : Net;
             begin
                if Left.Typ.W /= Right.Typ.W then
-                  Error_Msg_Synth
-                    (+Expr, "operands of ?/= don't have the same size");
+                  Error_Msg_Synth (Syn_Inst, Expr,
+                                   "operands of ?/= don't have the same size");
                   return Create_Value_Discrete (1, Bit_Type);
                end if;
 
@@ -1077,7 +1080,7 @@ package body Synth.Vhdl_Oper is
             return Synth_Int_Dyadic (Id_Srem);
          when Iir_Predefined_Integer_Exp =>
             Error_Msg_Synth
-              (+Expr, "non-constant exponentiation not supported");
+              (Syn_Inst, Expr, "non-constant exponentiation not supported");
             return No_Valtyp;
          when Iir_Predefined_Integer_Less_Equal =>
             return Synth_Compare (Id_Sle, Boolean_Type);
@@ -1092,11 +1095,13 @@ package body Synth.Vhdl_Oper is
          when Iir_Predefined_Integer_Inequality =>
             return Synth_Compare (Id_Ne, Boolean_Type);
          when Iir_Predefined_Physical_Physical_Div =>
-            Error_Msg_Synth (+Expr, "non-constant division not supported");
+            Error_Msg_Synth
+              (Syn_Inst, Expr, "non-constant division not supported");
             return No_Valtyp;
 
          when Iir_Predefined_Floating_Div =>
-            Error_Msg_Synth (+Expr, "non-constant division not supported");
+            Error_Msg_Synth
+              (Syn_Inst, Expr, "non-constant division not supported");
             return No_Valtyp;
 
          when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns
@@ -1618,8 +1623,9 @@ package body Synth.Vhdl_Oper is
             return Synth_Rotation (Id_Rol);
 
          when others =>
-            Error_Msg_Synth (+Expr, "synth_dyadic_operation: unhandled "
-                               & Iir_Predefined_Functions'Image (Def));
+            Error_Msg_Synth
+              (Syn_Inst, Expr, "synth_dyadic_operation: unhandled "
+                 & Iir_Predefined_Functions'Image (Def));
             return No_Valtyp;
       end case;
    end Synth_Dyadic_Operation;
@@ -1683,7 +1689,7 @@ package body Synth.Vhdl_Oper is
       if Is_Static_Val (Operand.Val) then
          return Create_Value_Memtyp
            (Eval_Static_Monadic_Predefined
-              (Imp, Get_Value_Memtyp (Operand), Loc));
+              (Syn_Inst, Imp, Get_Value_Memtyp (Operand), Loc));
       end if;
 
       case Def is
@@ -1761,7 +1767,7 @@ package body Synth.Vhdl_Oper is
 
          when others =>
             Error_Msg_Synth
-              (+Loc,
+              (Syn_Inst, Loc,
                "unhandled monadic: " & Iir_Predefined_Functions'Image (Def));
             return No_Valtyp;
       end case;
@@ -1905,7 +1911,9 @@ package body Synth.Vhdl_Oper is
          Size_Vt := Get_Value (Subprg_Inst, Param2);
          Strip_Const (Size_Vt);
          if not Is_Static (Size_Vt.Val) then
-            Error_Msg_Synth (+Expr, "size parameter must be constant");
+            Error_Msg_Synth
+              (Get_Caller_Instance (Subprg_Inst), Expr,
+               "size parameter must be constant");
             return No_Valtyp;
          end if;
          Size := Uns32 (Read_Discrete (Size_Vt));
@@ -2034,7 +2042,9 @@ package body Synth.Vhdl_Oper is
                W : Width;
             begin
                if not Is_Static (R.Val) then
-                  Error_Msg_Synth (+Expr, "size must be constant");
+                  Error_Msg_Synth
+                    (Get_Caller_Instance (Subprg_Inst), Expr,
+                     "size must be constant");
                   return No_Valtyp;
                end if;
                W := Uns32 (Read_Discrete (R));
@@ -2059,7 +2069,9 @@ package body Synth.Vhdl_Oper is
             | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn
             | Iir_Predefined_Ieee_Std_Logic_Arith_Sxt =>
             if not Is_Static (R.Val) then
-               Error_Msg_Synth (+Expr, "size must be constant");
+               Error_Msg_Synth
+                 (Get_Caller_Instance (Subprg_Inst), Expr,
+                  "size must be constant");
                return No_Valtyp;
             end if;
             return Synth_Resize
@@ -2140,12 +2152,14 @@ package body Synth.Vhdl_Oper is
                   Oper := L;
                else
                   Error_Msg_Synth
-                    (+Expr, "one operand of std_match must be constant");
+                    (Get_Caller_Instance (Subprg_Inst), Expr,
+                     "one operand of std_match must be constant");
                   return No_Valtyp;
                end if;
                if Oper.Typ.W /= Cst.Typ.W then
                   Error_Msg_Synth
-                    (+Expr, "operands of std_match don't have the same size");
+                    (Get_Caller_Instance (Subprg_Inst), Expr,
+                     "operands of std_match don't have the same size");
                   return Create_Value_Discrete (0, Boolean_Type);
                end if;
                Strip_Const (Cst);
@@ -2166,7 +2180,7 @@ package body Synth.Vhdl_Oper is
 
          when others =>
             Error_Msg_Synth
-              (+Expr,
+              (Get_Caller_Instance (Subprg_Inst), Expr,
                "unhandled function: " & Iir_Predefined_Functions'Image (Def));
             return No_Valtyp;
       end case;
@@ -2232,7 +2246,7 @@ package body Synth.Vhdl_Oper is
                Res_Typ := Get_Subtype_Object (Subprg_Inst, Get_Type (Imp));
 
                Mt := Eval_Static_Predefined_Function_Call
-                 (Param1, Param2, Res_Typ, Expr);
+                 (Syn_Inst, Param1, Param2, Res_Typ, Expr);
                if Mt /= Null_Memtyp then
                   Res := Create_Value_Memtyp (Mt);
                else
diff --git a/src/synth/synth-vhdl_static_proc.adb b/src/synth/synth-vhdl_static_proc.adb
index 585b16e58..d968a8631 100644
--- a/src/synth/synth-vhdl_static_proc.adb
+++ b/src/synth/synth-vhdl_static_proc.adb
@@ -110,7 +110,7 @@ package body Synth.Vhdl_Static_Proc is
             Synth_Textio_Write_Real (Syn_Inst, Imp);
          when others =>
             Error_Msg_Synth
-              (+Loc, "call to implicit %n is not supported", +Imp);
+              (Syn_Inst, Loc, "call to implicit %n is not supported", +Imp);
       end case;
    exception
       when File_Execution_Error =>
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb
index e7477b5bb..141ea05ff 100644
--- a/src/synth/synth-vhdl_stmts.adb
+++ b/src/synth/synth-vhdl_stmts.adb
@@ -249,7 +249,8 @@ package body Synth.Vhdl_Stmts is
                   else
                      --  Nested.
                      if Dest_Off /= (0, 0) then
-                        Error_Msg_Synth (+Pfx, "nested memory not supported");
+                        Error_Msg_Synth
+                          (Syn_Inst, Pfx, "nested memory not supported");
                      end if;
 
                      Dest_Dyn.Voff := Build_Addidx
@@ -613,7 +614,7 @@ package body Synth.Vhdl_Stmts is
          if not Is_Static (V.Val) then
             --  Maybe the error message is too cryptic ?
             Error_Msg_Synth
-              (+Loc, "cannot assign a net to a static value");
+              (Syn_Inst, Loc, "cannot assign a net to a static value");
          else
             Copy_Memory (Targ.Val.Mem + Off.Mem_Off, Get_Memory (V), V.Typ.Sz);
          end if;
@@ -2096,7 +2097,7 @@ package body Synth.Vhdl_Stmts is
                   if not Is_Scalar_Subtype_Compatible (Val.Typ, Inter_Typ)
                   then
                      Error_Msg_Synth
-                       (+Actual,
+                       (Caller_Inst, Actual,
                         "scalar subtype of actual is not compatible with "
                           & "signal formal interface");
                   end if;
@@ -2105,7 +2106,7 @@ package body Synth.Vhdl_Stmts is
                   if not Is_Scalar_Subtype_Compatible (Inter_Typ, Val.Typ)
                   then
                      Error_Msg_Synth
-                       (+Actual,
+                       (Caller_Inst, Actual,
                         "signal formal interface scalar subtype is not "
                           & "compatible with of actual subtype");
                   end if;
@@ -2546,7 +2547,7 @@ package body Synth.Vhdl_Stmts is
          if Is_Func then
             if C.Nbr_Ret = 0 then
                Error_Msg_Synth
-                 (+Bod, "missing return statement at end of function");
+                 (C.Inst, Bod, "missing return statement at end of function");
                Res := No_Valtyp;
             elsif C.Nbr_Ret = 1 and then Is_Static (C.Ret_Value.Val) then
                Res := C.Ret_Value;
@@ -2624,7 +2625,8 @@ package body Synth.Vhdl_Stmts is
          if Is_Func then
             if C.Nbr_Ret = 0 then
                Error_Msg_Synth
-                 (+Loc, "function call completed without a return statement");
+                 (C.Inst, Loc,
+                  "function call completed without a return statement");
                Res := No_Valtyp;
             else
                pragma Assert (C.Nbr_Ret = 1);
@@ -2855,7 +2857,7 @@ package body Synth.Vhdl_Stmts is
          when Iir_Predefined_None =>
             if Get_Foreign_Flag (Imp) then
                Error_Msg_Synth
-                 (+Stmt, "call to foreign %n is not supported", +Imp);
+                 (Syn_Inst, Stmt, "call to foreign %n is not supported", +Imp);
             else
                Res := Synth_Subprogram_Call (Syn_Inst, Call);
                pragma Assert (Res = No_Valtyp);
@@ -3352,7 +3354,7 @@ package body Synth.Vhdl_Stmts is
             Mark_Expr_Pool (Marker);
             Val := Synth_Expression_With_Type (C.Inst, Cond, Boolean_Type);
             if not Is_Static (Val.Val) then
-               Error_Msg_Synth (+Cond, "loop condition must be static");
+               Error_Msg_Synth (C.Inst, Cond, "loop condition must be static");
                Release_Expr_Pool (Marker);
                exit;
             end if;
@@ -3373,7 +3375,7 @@ package body Synth.Vhdl_Stmts is
          Iter_Nbr := Iter_Nbr + 1;
          if Iter_Nbr > Flags.Flag_Max_Loop and Flags.Flag_Max_Loop /= 0 then
             Error_Msg_Synth
-              (+Stmt, "maximum number of iterations (%v) reached",
+              (C.Inst, Stmt, "maximum number of iterations (%v) reached",
                +Uns32 (Flags.Flag_Max_Loop));
             exit;
          end if;
@@ -3574,8 +3576,7 @@ package body Synth.Vhdl_Stmts is
       Release_Expr_Pool (Marker);
 
       if Sev_V >= Flags.Severity_Level then
-         Error_Msg_Synth (+Stmt, "error due to assertion failure");
-         Elab.Debugger.Debug_Error (Syn_Inst, Stmt);
+         Error_Msg_Synth (Syn_Inst, Stmt, "error due to assertion failure");
       end if;
    end Exec_Failed_Assertion;
 
@@ -3771,7 +3772,7 @@ package body Synth.Vhdl_Stmts is
                end if;
             when Iir_Kind_Wait_Statement =>
                Error_Msg_Synth
-                 (+Stmt, "wait statement not allowed for synthesis");
+                 (C.Inst, Stmt, "wait statement not allowed for synthesis");
             when others =>
                Error_Kind ("synth_sequential_statements", Stmt);
          end case;
@@ -3814,7 +3815,7 @@ package body Synth.Vhdl_Stmts is
 
       --  The first statement must be a wait statement.
       if Get_Kind (Stmt) /= Iir_Kind_Wait_Statement then
-         Error_Msg_Synth (+Stmt, "expect wait as the first statement");
+         Error_Msg_Synth (C.Inst, Stmt, "expect wait as the first statement");
          return;
       end if;
 
@@ -3823,7 +3824,7 @@ package body Synth.Vhdl_Stmts is
       --  Handle the condition as an if.
       Cond := Get_Condition_Clause (Stmt);
       if Cond = Null_Node then
-         Error_Msg_Synth (+Stmt, "expect wait condition");
+         Error_Msg_Synth (C.Inst, Stmt, "expect wait condition");
          return;
       end if;
       Cond_Val := Synth_Expression (C.Inst, Cond);
@@ -3924,8 +3925,8 @@ package body Synth.Vhdl_Stmts is
             if Get_Kind (Unit) = Iir_Kind_Design_Unit then
                Lib := Get_Library (Get_Design_File (Unit));
                if Get_Identifier (Lib) = Std_Names.Name_Ieee then
-                  Error_Msg_Synth
-                    (+Expr, "unhandled call to ieee function %i", +Imp);
+                  Error_Msg_Synth (Syn_Inst, Expr,
+                                   "unhandled call to ieee function %i", +Imp);
                   Set_Error (Syn_Inst);
                   return No_Valtyp;
                end if;
@@ -4084,7 +4085,7 @@ package body Synth.Vhdl_Stmts is
       --  Check the clock is an edge and extract it.
       Clk_Inst := Get_Net_Parent (Clk);
       if Get_Id (Clk_Inst) not in Edge_Module_Id then
-         Error_Msg_Synth (+Stmt, "clock is not an edge");
+         Error_Msg_Synth (Syn_Inst, Stmt, "clock is not an edge");
          Next_States := No_Net;
          Release_Expr_Pool (Marker);
          return;
@@ -4459,15 +4460,17 @@ package body Synth.Vhdl_Stmts is
       if (Get_Base_Type (Get_Type (Val)) /=
             Vhdl.Std_Package.Boolean_Type_Definition)
       then
-         Error_Msg_Synth (+Val, "type of attribute %i must be boolean",
-                          (1 => +Get_Attribute_Designator (Spec)));
+         Error_Msg_Synth
+           (Syn_Inst, Val, "type of attribute %i must be boolean",
+            (1 => +Get_Attribute_Designator (Spec)));
          return;
       end if;
 
       --  The designated entity must be a signal.
       if Get_Kind (Sig) /= Iir_Kind_Signal_Declaration then
-         Error_Msg_Synth (+Val, "attribute %i only applies to signals",
-                          (1 => +Get_Attribute_Designator (Spec)));
+         Error_Msg_Synth
+           (Syn_Inst, Val, "attribute %i only applies to signals",
+            (1 => +Get_Attribute_Designator (Spec)));
          return;
       end if;
 
diff --git a/src/vhdl/vhdl-evaluation.adb b/src/vhdl/vhdl-evaluation.adb
index c4cbcae50..65e12cabe 100644
--- a/src/vhdl/vhdl-evaluation.adb
+++ b/src/vhdl/vhdl-evaluation.adb
@@ -1035,10 +1035,10 @@ package body Vhdl.Evaluation is
       if Right /= Null_Iir then
          Right_Mt := Convert_Node_To_Memtyp (Right);
          Res_Mt := Eval_Static_Dyadic_Predefined
-           (Imp, Res_Typ, Left_Mt, Right_Mt, Orig);
+           (null, Imp, Res_Typ, Left_Mt, Right_Mt, Orig);
       else
          Res_Mt := Eval_Static_Monadic_Predefined
-           (Imp, Left_Mt, Orig);
+           (null, Imp, Left_Mt, Orig);
       end if;
       Res := Convert_Memtyp_To_Node (Res_Mt, Res_Type, Orig);
       Release_Expr_Pool (Marker);