diff options
| -rw-r--r-- | src/psl/psl-build.adb | 3 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 6 | ||||
| -rw-r--r-- | src/vhdl/vhdl-annotations.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/vhdl-canon.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_psl.adb | 2 |
5 files changed, 12 insertions, 4 deletions
diff --git a/src/psl/psl-build.adb b/src/psl/psl-build.adb index b9a0ccf9b..451466608 100644 --- a/src/psl/psl-build.adb +++ b/src/psl/psl-build.adb @@ -973,7 +973,8 @@ package body PSL.Build is begin case Get_Kind (N) is when N_Sequences - | N_Booleans => + | N_Booleans + | N_Sequence_Instance => -- Build A(S) or A(B) R := Build_SERE_FA (N); return Determinize.Determinize (R); diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 687be6510..d54cabf76 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -3823,7 +3823,8 @@ package body Synth.Vhdl_Stmts is Item := Get_Vunit_Item_Chain (Unit); while Item /= Null_Node loop case Get_Kind (Item) is - when Iir_Kind_Psl_Default_Clock => + when Iir_Kind_Psl_Default_Clock + | Iir_Kind_Psl_Declaration => null; when Iir_Kind_Psl_Assert_Directive => Synth_Psl_Assert_Directive (Unit_Inst, Item); @@ -3865,7 +3866,8 @@ package body Synth.Vhdl_Stmts is | Iir_Kind_Psl_Assert_Directive | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Restrict_Directive - | Iir_Kind_Psl_Cover_Directive => + | Iir_Kind_Psl_Cover_Directive + | Iir_Kind_Psl_Declaration => null; when Iir_Kinds_Concurrent_Signal_Assignment | Iir_Kinds_Process_Statement diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index 36a61238e..fae87203a 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -1138,7 +1138,8 @@ package body Vhdl.Annotations is Item := Get_Vunit_Item_Chain (Decl); while Item /= Null_Iir loop case Get_Kind (Item) is - when Iir_Kind_Psl_Default_Clock => + when Iir_Kind_Psl_Default_Clock + | Iir_Kind_Psl_Declaration => null; when Iir_Kind_Psl_Assert_Directive | Iir_Kind_Psl_Assume_Directive diff --git a/src/vhdl/vhdl-canon.adb b/src/vhdl/vhdl-canon.adb index 563668125..ddaed3792 100644 --- a/src/vhdl/vhdl-canon.adb +++ b/src/vhdl/vhdl-canon.adb @@ -3422,6 +3422,8 @@ package body Vhdl.Canon is Canon_Psl_Sequence_Directive (Item); when Iir_Kind_Psl_Cover_Directive => Canon_Psl_Cover_Directive (Item); + when Iir_Kind_Psl_Declaration => + Canon_Concurrent_Statement (Item, Unit); when Iir_Kind_Signal_Declaration | Iir_Kind_Constant_Declaration | Iir_Kind_Type_Declaration diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb index 51fcc8766..c000c1a47 100644 --- a/src/vhdl/vhdl-sem_psl.adb +++ b/src/vhdl/vhdl-sem_psl.adb @@ -1179,6 +1179,8 @@ package body Vhdl.Sem_Psl is Sem_Psl_Restrict_Directive (Item); when Iir_Kind_Psl_Cover_Directive => Sem_Psl_Cover_Directive (Item); + when Iir_Kind_Psl_Declaration => + Sem_Psl_Declaration (Item); when Iir_Kind_Signal_Declaration | Iir_Kind_Constant_Declaration | Iir_Kind_Type_Declaration |