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author | Tristan Gingold <tgingold@free.fr> | 2019-05-04 22:12:13 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-05-04 22:12:13 +0200 |
commit | 19a9154fb3fadd0a33a6826e525091a9a75687e4 (patch) | |
tree | 194672b3beb90cbebc64ecad413c49728253d1da /src/vhdl/simulate/simul-debugger.adb | |
parent | bddf80741a2a4f574e9b531c046a531d0d53ea86 (diff) | |
download | ghdl-19a9154fb3fadd0a33a6826e525091a9a75687e4.tar.gz ghdl-19a9154fb3fadd0a33a6826e525091a9a75687e4.tar.bz2 ghdl-19a9154fb3fadd0a33a6826e525091a9a75687e4.zip |
vhdl: move disp_tree and disp_vhdl as vhdl child.
Diffstat (limited to 'src/vhdl/simulate/simul-debugger.adb')
-rw-r--r-- | src/vhdl/simulate/simul-debugger.adb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vhdl/simulate/simul-debugger.adb b/src/vhdl/simulate/simul-debugger.adb index 82eec793e..c43c96df9 100644 --- a/src/vhdl/simulate/simul-debugger.adb +++ b/src/vhdl/simulate/simul-debugger.adb @@ -37,7 +37,7 @@ with Simul.Elaboration; use Simul.Elaboration; with Simul.Execution; use Simul.Execution; with Iirs_Utils; use Iirs_Utils; with Errorout; use Errorout; -with Disp_Vhdl; +with Vhdl.Disp_Vhdl; with Iirs_Walk; use Iirs_Walk; with Areapools; use Areapools; with Grt.Types; use Grt.Types; @@ -1521,7 +1521,7 @@ package body Simul.Debugger is Put ('.'); Put (Name_Table.Image (Get_Identifier (E.Stmt))); New_Line; - Disp_Vhdl.Disp_PSL_NFA (Get_PSL_NFA (E.Stmt)); + Vhdl.Disp_Vhdl.Disp_PSL_NFA (Get_PSL_NFA (E.Stmt)); Put (" 01234567890123456789012345678901234567890123456789"); for I in E.States'Range loop if I mod 50 = 0 then @@ -1925,7 +1925,7 @@ package body Simul.Debugger is return; end if; - Disp_Vhdl.Disp_Expression (Expr); + Vhdl.Disp_Vhdl.Disp_Expression (Expr); New_Line; Annotate_Expand_Table; |