diff options
| author | Tristan Gingold <tgingold@free.fr> | 2019-05-04 22:12:13 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-05-04 22:12:13 +0200 |
| commit | 19a9154fb3fadd0a33a6826e525091a9a75687e4 (patch) | |
| tree | 194672b3beb90cbebc64ecad413c49728253d1da /src/vhdl/simulate | |
| parent | bddf80741a2a4f574e9b531c046a531d0d53ea86 (diff) | |
| download | ghdl-19a9154fb3fadd0a33a6826e525091a9a75687e4.tar.gz ghdl-19a9154fb3fadd0a33a6826e525091a9a75687e4.tar.bz2 ghdl-19a9154fb3fadd0a33a6826e525091a9a75687e4.zip | |
vhdl: move disp_tree and disp_vhdl as vhdl child.
Diffstat (limited to 'src/vhdl/simulate')
| -rw-r--r-- | src/vhdl/simulate/simul-debugger-ams.adb | 4 | ||||
| -rw-r--r-- | src/vhdl/simulate/simul-debugger.adb | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/vhdl/simulate/simul-debugger-ams.adb b/src/vhdl/simulate/simul-debugger-ams.adb index 2c7c86316..ab4cfa36b 100644 --- a/src/vhdl/simulate/simul-debugger-ams.adb +++ b/src/vhdl/simulate/simul-debugger-ams.adb @@ -18,7 +18,7 @@ with Iirs_Utils; use Iirs_Utils; with Ada.Text_IO; use Ada.Text_IO; -with Disp_Vhdl; +with Vhdl.Disp_Vhdl; package body Simul.Debugger.AMS is procedure Disp_Quantity_Name (Quantity : Quantity_Index_Type) @@ -46,7 +46,7 @@ package body Simul.Debugger.AMS is when Op_Quantity => Disp_Quantity_Name (Term.Quantity); when Op_Vhdl_Expr => - Disp_Vhdl.Disp_Expression (Term.Vhdl_Expr); + Vhdl.Disp_Vhdl.Disp_Expression (Term.Vhdl_Expr); end case; end Disp_Term; diff --git a/src/vhdl/simulate/simul-debugger.adb b/src/vhdl/simulate/simul-debugger.adb index 82eec793e..c43c96df9 100644 --- a/src/vhdl/simulate/simul-debugger.adb +++ b/src/vhdl/simulate/simul-debugger.adb @@ -37,7 +37,7 @@ with Simul.Elaboration; use Simul.Elaboration; with Simul.Execution; use Simul.Execution; with Iirs_Utils; use Iirs_Utils; with Errorout; use Errorout; -with Disp_Vhdl; +with Vhdl.Disp_Vhdl; with Iirs_Walk; use Iirs_Walk; with Areapools; use Areapools; with Grt.Types; use Grt.Types; @@ -1521,7 +1521,7 @@ package body Simul.Debugger is Put ('.'); Put (Name_Table.Image (Get_Identifier (E.Stmt))); New_Line; - Disp_Vhdl.Disp_PSL_NFA (Get_PSL_NFA (E.Stmt)); + Vhdl.Disp_Vhdl.Disp_PSL_NFA (Get_PSL_NFA (E.Stmt)); Put (" 01234567890123456789012345678901234567890123456789"); for I in E.States'Range loop if I mod 50 = 0 then @@ -1925,7 +1925,7 @@ package body Simul.Debugger is return; end if; - Disp_Vhdl.Disp_Expression (Expr); + Vhdl.Disp_Vhdl.Disp_Expression (Expr); New_Line; Annotate_Expand_Table; |