From 19a9154fb3fadd0a33a6826e525091a9a75687e4 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 4 May 2019 22:12:13 +0200
Subject: vhdl: move disp_tree and disp_vhdl as vhdl child.

---
 src/vhdl/simulate/simul-debugger.adb | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/vhdl/simulate/simul-debugger.adb')

diff --git a/src/vhdl/simulate/simul-debugger.adb b/src/vhdl/simulate/simul-debugger.adb
index 82eec793e..c43c96df9 100644
--- a/src/vhdl/simulate/simul-debugger.adb
+++ b/src/vhdl/simulate/simul-debugger.adb
@@ -37,7 +37,7 @@ with Simul.Elaboration; use Simul.Elaboration;
 with Simul.Execution; use Simul.Execution;
 with Iirs_Utils; use Iirs_Utils;
 with Errorout; use Errorout;
-with Disp_Vhdl;
+with Vhdl.Disp_Vhdl;
 with Iirs_Walk; use Iirs_Walk;
 with Areapools; use Areapools;
 with Grt.Types; use Grt.Types;
@@ -1521,7 +1521,7 @@ package body Simul.Debugger is
             Put ('.');
             Put (Name_Table.Image (Get_Identifier (E.Stmt)));
             New_Line;
-            Disp_Vhdl.Disp_PSL_NFA (Get_PSL_NFA (E.Stmt));
+            Vhdl.Disp_Vhdl.Disp_PSL_NFA (Get_PSL_NFA (E.Stmt));
             Put ("    01234567890123456789012345678901234567890123456789");
             for I in E.States'Range loop
                if I mod 50 = 0 then
@@ -1925,7 +1925,7 @@ package body Simul.Debugger is
          return;
       end if;
 
-      Disp_Vhdl.Disp_Expression (Expr);
+      Vhdl.Disp_Vhdl.Disp_Expression (Expr);
       New_Line;
 
       Annotate_Expand_Table;
-- 
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