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authorTristan Gingold <tgingold@free.fr>2017-12-19 18:11:42 +0100
committerTristan Gingold <tgingold@free.fr>2017-12-21 07:36:46 +0100
commit787ef6f900f18ea853c01edaf00f0e6836b61834 (patch)
tree35dda8ea46fd47ed20784acac2b494af4267d2ee /src/vhdl/simulate/simul-annotations.adb
parent07fca900ea7744f45044b93dcac6887671ad93f6 (diff)
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simul: fix issue228.
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