vhdl: move std_standard package to vhdl child.

41 files changed, 90 insertions, 89 deletions

diff --git a/src/ghdldrv/ghdlcomp.adb b/src/ghdldrv/ghdlcomp.adb
index 2ac085d9c..542042819 100644
--- a/src/ghdldrv/ghdlcomp.adb
+++ b/src/ghdldrv/ghdlcomp.adb
@@ -29,7 +29,7 @@ with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
 with Name_Table;
 with Errorout; use Errorout;
 with Libraries;
-with Std_Package;
+with Vhdl.Std_Package;
 with Files_Map;
 with Version;
 
@@ -682,7 +682,7 @@ package body Ghdlcomp is
       while Is_Valid (It) loop
          File := Get_Element (It);
 
-         if File = Std_Package.Std_Standard_File then
+         if File = Vhdl.Std_Package.Std_Standard_File then
             null;
          elsif Source_File_Modified (File)
            or else Is_File_Outdated (File)
@@ -778,7 +778,7 @@ package body Ghdlcomp is
 
    function Is_Makeable_File (File : Iir_Design_File) return Boolean is
    begin
-      if File = Std_Package.Std_Standard_File then
+      if File = Vhdl.Std_Package.Std_Standard_File then
          return False;
       end if;
       return True;
diff --git a/src/ghdldrv/ghdllocal.adb b/src/ghdldrv/ghdllocal.adb
index a400ff69d..8b261279b 100644
--- a/src/ghdldrv/ghdllocal.adb
+++ b/src/ghdldrv/ghdllocal.adb
@@ -21,7 +21,7 @@ with GNAT.Directory_Operations;
 with Types; use Types;
 with Libraries;
 with Vhdl.Sem_Lib;
-with Std_Package;
+with Vhdl.Std_Package;
 with Flags;
 with Name_Table;
 with Std_Names;
@@ -1116,7 +1116,7 @@ package body Ghdllocal is
       end if;
       Flags.Bootstrap := True;
       Libraries.Load_Std_Library;
-      Vhdl.Disp_Vhdl.Disp_Vhdl (Std_Package.Std_Standard_Unit);
+      Vhdl.Disp_Vhdl.Disp_Vhdl (Vhdl.Std_Package.Std_Standard_Unit);
    end Perform_Action;
 
    --  Command --find-top.
@@ -1527,7 +1527,7 @@ package body Ghdllocal is
                         return True;
                      end if;
                      Dep_File := Get_Design_File (Dep);
-                     if Dep /= Std_Package.Std_Standard_Unit
+                     if Dep /= Vhdl.Std_Package.Std_Standard_Unit
                        and then
                        Files_Map.Is_Gt (Get_Analysis_Time_Stamp (Dep_File),
                                         Stamp)
diff --git a/src/ghdldrv/ghdlrun.adb b/src/ghdldrv/ghdlrun.adb
index 6763498f7..f8b3adaaf 100644
--- a/src/ghdldrv/ghdlrun.adb
+++ b/src/ghdldrv/ghdlrun.adb
@@ -32,7 +32,7 @@ with Ortho_Jit;
 with Ortho_Nodes; use Ortho_Nodes;
 with Trans_Decls;
 with Iirs; use Iirs;
-with Std_Package;
+with Vhdl.Std_Package;
 with Flags;
 with Errorout; use Errorout;
 with Libraries;
@@ -128,7 +128,7 @@ package body Ghdlrun is
       end if;
 
       if Time_Resolution /= 'a' then
-         Std_Package.Set_Time_Resolution (Time_Resolution);
+         Vhdl.Std_Package.Set_Time_Resolution (Time_Resolution);
       end if;
 
       if Analyze_Only then
@@ -173,7 +173,7 @@ package body Ghdlrun is
       end if;
 
       if Time_Resolution = 'a' then
-         Time_Resolution := Std_Package.Get_Minimal_Time_Resolution;
+         Time_Resolution := Vhdl.Std_Package.Get_Minimal_Time_Resolution;
          if Time_Resolution = '?' then
             Time_Resolution := 'f';
          end if;
@@ -195,7 +195,7 @@ package body Ghdlrun is
             end;
          end if;
       end if;
-      Std_Package.Set_Time_Resolution (Time_Resolution);
+      Vhdl.Std_Package.Set_Time_Resolution (Time_Resolution);
 
       --  Overwrite time resolution in flag string.
       Flags.Flag_String (5) := Time_Resolution;
diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb
index cc968048f..b465ed8cc 100644
--- a/src/ghdldrv/ghdlsimul.adb
+++ b/src/ghdldrv/ghdlsimul.adb
@@ -26,7 +26,7 @@ with Types;
 with Flags;
 with Name_Table;
 with Errorout; use Errorout;
-with Std_Package;
+with Vhdl.Std_Package;
 with Libraries;
 with Vhdl.Canon;
 with Vhdl.Configuration;
@@ -61,14 +61,14 @@ package body Ghdlsimul is
       end if;
 
       if Time_Resolution /= 'a' then
-         Std_Package.Set_Time_Resolution (Time_Resolution);
+         Vhdl.Std_Package.Set_Time_Resolution (Time_Resolution);
       end if;
 
       if Analyze_Only then
          return;
       end if;
 
-      Simul.Annotations.Annotate (Std_Package.Std_Standard_Unit);
+      Simul.Annotations.Annotate (Vhdl.Std_Package.Std_Standard_Unit);
 
       Vhdl.Canon.Canon_Flag_Add_Labels := True;
       Vhdl.Canon.Canon_Flag_Sequentials_Stmts := True;
diff --git a/src/libraries.adb b/src/libraries.adb
index bf0d63503..716438ca6 100644
--- a/src/libraries.adb
+++ b/src/libraries.adb
@@ -28,7 +28,7 @@ with Str_Table;
 with Vhdl.Tokens;
 with Files_Map;
 with Flags;
-with Std_Package;
+with Vhdl.Std_Package;
 
 package body Libraries is
    --  Chain of known libraries.  This is also the top node of all iir node.
@@ -626,7 +626,7 @@ package body Libraries is
    -- Note: the scanner shouldn't be in use, since this procedure uses it.
    procedure Load_Std_Library (Build_Standard : Boolean := True)
    is
-      use Std_Package;
+      use Vhdl.Std_Package;
       Dir : Name_Id;
    begin
       if Libraries_Chain /= Null_Iir then
@@ -637,7 +637,7 @@ package body Libraries is
       Flags.Create_Flag_String;
       Create_Virtual_Locations;
 
-      Std_Package.Create_First_Nodes;
+      Vhdl.Std_Package.Create_First_Nodes;
 
       --  Create the library.
       Std_Library := Create_Iir (Iir_Kind_Library_Declaration);
@@ -1325,7 +1325,7 @@ package body Libraries is
       Design_File := Get_Design_File_Chain (Library);
       while Design_File /= Null_Iir loop
          --  Ignore std.standard as there is no corresponding file.
-         if Design_File = Std_Package.Std_Standard_File then
+         if Design_File = Vhdl.Std_Package.Std_Standard_File then
             goto Continue;
          end if;
          Design_Unit := Get_First_Design_Unit (Design_File);
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb
index 96242ee73..607c94555 100644
--- a/src/synth/synth-context.adb
+++ b/src/synth/synth-context.adb
@@ -25,7 +25,7 @@ with Grt.Types; use Grt.Types;
 with Errorout; use Errorout;
 with Iirs_Utils;
 
-with Std_Package;
+with Vhdl.Std_Package;
 with Ieee.Std_Logic_1164;
 
 with Simul.Annotations; use Simul.Annotations;
@@ -139,8 +139,9 @@ package body Synth.Context is
             case Val.Lit.Kind is
                when Iir_Value_B1 =>
                   pragma Assert
-                    (Val.Lit_Type = Std_Package.Boolean_Type_Definition
-                       or else Val.Lit_Type = Std_Package.Bit_Type_Definition);
+                    (Val.Lit_Type = Vhdl.Std_Package.Boolean_Type_Definition
+                       or else
+                       Val.Lit_Type = Vhdl.Std_Package.Bit_Type_Definition);
                   return Build_Const_UB32
                     (Build_Context, Ghdl_B1'Pos (Val.Lit.B1), 1);
                when Iir_Value_E8 =>
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index dea474e6c..cbc9f87d2 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -22,7 +22,7 @@ with Ada.Unchecked_Conversion;
 with Ada.Unchecked_Deallocation;
 with Std_Names;
 with Ieee.Std_Logic_1164;
-with Std_Package;
+with Vhdl.Std_Package;
 with Errorout; use Errorout;
 with Simul.Execution;
 with Grt.Types; use Grt.Types;
@@ -695,11 +695,11 @@ package body Synth.Expr is
          return Build_Edge (Build_Context, True, Clk);
       end if;
       Lit := Get_Named_Entity (Right);
-      if Lit = Std_Package.Bit_0
+      if Lit = Vhdl.Std_Package.Bit_0
         or else Lit = Ieee.Std_Logic_1164.Std_Ulogic_0
       then
          Posedge := False;
-      elsif Lit = Std_Package.Bit_1
+      elsif Lit = Vhdl.Std_Package.Bit_1
         or else Lit = Ieee.Std_Logic_1164.Std_Ulogic_1
       then
          Posedge := True;
diff --git a/src/synth/synth-types.adb b/src/synth/synth-types.adb
index 87fc1826c..88542ab6b 100644
--- a/src/synth/synth-types.adb
+++ b/src/synth/synth-types.adb
@@ -19,7 +19,7 @@
 --  MA 02110-1301, USA.
 
 with Types; use Types;
-with Std_Package;
+with Vhdl.Std_Package;
 with Ieee.Std_Logic_1164;
 with Iirs_Utils; use Iirs_Utils;
 
@@ -32,8 +32,8 @@ package body Synth.Types is
    begin
       return Atype = Ieee.Std_Logic_1164.Std_Ulogic_Type
         or else Atype = Ieee.Std_Logic_1164.Std_Logic_Type
-        or else Atype = Std_Package.Boolean_Type_Definition
-        or else Atype = Std_Package.Bit_Type_Definition;
+        or else Atype = Vhdl.Std_Package.Boolean_Type_Definition
+        or else Atype = Vhdl.Std_Package.Bit_Type_Definition;
    end Is_Bit_Type;
 
    function Is_Vector_Type (Atype : Iir) return Boolean is
diff --git a/src/vhdl/evaluation.adb b/src/vhdl/evaluation.adb
index ec366aeef..a3355f7a6 100644
--- a/src/vhdl/evaluation.adb
+++ b/src/vhdl/evaluation.adb
@@ -22,7 +22,7 @@ with Errorout; use Errorout;
 with Name_Table; use Name_Table;
 with Str_Table;
 with Iirs_Utils; use Iirs_Utils;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Flags; use Flags;
 with Std_Names;
 with Ada.Characters.Handling;
diff --git a/src/vhdl/ieee-numeric.adb b/src/vhdl/ieee-numeric.adb
index d87cb1898..c6dfcb17a 100644
--- a/src/vhdl/ieee-numeric.adb
+++ b/src/vhdl/ieee-numeric.adb
@@ -17,7 +17,7 @@
 --  02111-1307, USA.
 
 with Types; use Types;
-with Std_Package;
+with Vhdl.Std_Package;
 with Std_Names; use Std_Names;
 with Errorout; use Errorout;
 with Ieee.Std_Logic_1164;
@@ -88,10 +88,10 @@ package body Ieee.Numeric is
          elsif Arg_Type = Unsigned_Type then
             Sign := Type_Unsigned;
             Kind := Arg_Vect;
-         elsif Arg_Type = Std_Package.Integer_Subtype_Definition then
+         elsif Arg_Type = Vhdl.Std_Package.Integer_Subtype_Definition then
             Sign := Type_Signed;
             Kind := Arg_Scal;
-         elsif Arg_Type = Std_Package.Natural_Subtype_Definition then
+         elsif Arg_Type = Vhdl.Std_Package.Natural_Subtype_Definition then
             Sign := Type_Unsigned;
             Kind := Arg_Scal;
          elsif Arg_Type = Ieee.Std_Logic_1164.Std_Ulogic_Type then
@@ -157,7 +157,7 @@ package body Ieee.Numeric is
       if Decl /= Null_Iir
         and then Get_Kind (Decl) = Iir_Kind_Constant_Declaration
         and then (Get_Base_Type (Get_Type (Decl))
-                  = Std_Package.String_Type_Definition)
+                  = Vhdl.Std_Package.String_Type_Definition)
       then
          Decl := Get_Chain (Decl);
       end if;
diff --git a/src/vhdl/ieee-vital_timing.adb b/src/vhdl/ieee-vital_timing.adb
index a1413285e..d4777d651 100644
--- a/src/vhdl/ieee-vital_timing.adb
+++ b/src/vhdl/ieee-vital_timing.adb
@@ -18,7 +18,7 @@
 with Types; use Types;
 with Std_Names;
 with Errorout; use Errorout;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Vhdl.Tokens; use Vhdl.Tokens;
 with Name_Table;
 with Ieee.Std_Logic_1164; use Ieee.Std_Logic_1164;
diff --git a/src/vhdl/ieee.adb b/src/vhdl/ieee.adb
index d730bf388..393a05d32 100644
--- a/src/vhdl/ieee.adb
+++ b/src/vhdl/ieee.adb
@@ -17,7 +17,7 @@
 --  02111-1307, USA.
 
 with Iirs_Utils; use Iirs_Utils;
-with Std_Package;
+with Vhdl.Std_Package;
 
 package body Ieee is
    function Skip_Copyright_Notice (Decl : Iir) return Iir
@@ -26,7 +26,7 @@ package body Ieee is
       if Decl /= Null_Iir
         and then Get_Kind (Decl) = Iir_Kind_Constant_Declaration
         and then (Get_Base_Type (Get_Type (Decl))
-                    = Std_Package.String_Type_Definition)
+                    = Vhdl.Std_Package.String_Type_Definition)
       then
          return Get_Chain (Decl);
       else
diff --git a/src/vhdl/iirs_utils.adb b/src/vhdl/iirs_utils.adb
index 034fdd051..89b9d46ec 100644
--- a/src/vhdl/iirs_utils.adb
+++ b/src/vhdl/iirs_utils.adb
@@ -21,7 +21,7 @@ with Errorout; use Errorout;
 with Name_Table;
 with Str_Table;
 with Std_Names; use Std_Names;
-with Std_Package;
+with Vhdl.Std_Package;
 with Flags; use Flags;
 with PSL.Nodes;
 
@@ -1358,7 +1358,7 @@ package body Iirs_Utils is
       Name : constant Iir := Get_Entity_Name (Decl);
       Res : constant Iir := Get_Named_Entity (Name);
    begin
-      if Res = Std_Package.Error_Mark then
+      if Res = Vhdl.Std_Package.Error_Mark then
          return Null_Iir;
       end if;
 
diff --git a/src/vhdl/nodes_gc.adb b/src/vhdl/nodes_gc.adb
index 1ee3696ab..eb7d4dee3 100644
--- a/src/vhdl/nodes_gc.adb
+++ b/src/vhdl/nodes_gc.adb
@@ -24,7 +24,7 @@ with Nodes_Meta; use Nodes_Meta;
 with Errorout; use Errorout;
 with Libraries;
 with Vhdl.Disp_Tree;
-with Std_Package;
+with Vhdl.Std_Package;
 
 package body Nodes_GC is
 
@@ -375,7 +375,7 @@ package body Nodes_GC is
    --  but referenced nodes in std_package.
    procedure Mark_Init
    is
-      use Std_Package;
+      use Vhdl.Std_Package;
    begin
       Markers := new Marker_Array'(Null_Iir .. Iirs.Get_Last_Node => False);
 
@@ -389,7 +389,7 @@ package body Nodes_GC is
    --  Marks known nodes that aren't owned.
    procedure Mark_Not_Owned
    is
-      use Std_Package;
+      use Vhdl.Std_Package;
    begin
       --  These nodes are owned by type/subtype declarations, so unmark them
       --  before marking their owner.
@@ -478,7 +478,7 @@ package body Nodes_GC is
 
    procedure Report_Unreferenced
    is
-      use Std_Package;
+      use Vhdl.Std_Package;
       El : Iir;
       Nbr_Unreferenced : Natural;
    begin
diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/simulate/simul-annotations.adb
index f02f642b1..22ca12a07 100644
--- a/src/vhdl/simulate/simul-annotations.adb
+++ b/src/vhdl/simulate/simul-annotations.adb
@@ -18,7 +18,7 @@
 
 with Tables;
 with Ada.Text_IO;
-with Std_Package;
+with Vhdl.Std_Package;
 with Errorout; use Errorout;
 with Iirs_Utils; use Iirs_Utils;
 with Types; use Types;
@@ -279,8 +279,8 @@ package body Simul.Annotations is
             declare
                Mode : Iir_Value_Kind;
             begin
-               if Def = Std_Package.Boolean_Type_Definition
-                 or else Def = Std_Package.Bit_Type_Definition
+               if Def = Vhdl.Std_Package.Boolean_Type_Definition
+                 or else Def = Vhdl.Std_Package.Bit_Type_Definition
                then
                   Mode := Iir_Value_B1;
                elsif (Get_Nbr_Elements (Get_Enumeration_Literal_List (Def))
@@ -1161,7 +1161,7 @@ package body Simul.Annotations is
             Annotate_Architecture (El);
          when Iir_Kind_Package_Declaration =>
             declare
-               use Std_Package;
+               use Vhdl.Std_Package;
             begin
                if El = Standard_Package then
                   pragma Assert (Global_Info = null);
diff --git a/src/vhdl/simulate/simul-debugger.adb b/src/vhdl/simulate/simul-debugger.adb
index 8c911a706..e96a8100e 100644
--- a/src/vhdl/simulate/simul-debugger.adb
+++ b/src/vhdl/simulate/simul-debugger.adb
@@ -31,7 +31,7 @@ with Vhdl.Sem_Scopes;
 with Vhdl.Canon;
 with Std_Names;
 with Libraries;
-with Std_Package;
+with Vhdl.Std_Package;
 with Simul.Annotations; use Simul.Annotations;
 with Simul.Elaboration; use Simul.Elaboration;
 with Simul.Execution; use Simul.Execution;
@@ -1826,7 +1826,7 @@ package body Simul.Debugger is
 
       --  Add STD
       Add_Name (Libraries.Std_Library, Std_Names.Name_Std, False);
-      Use_All_Names (Std_Package.Standard_Package);
+      Use_All_Names (Vhdl.Std_Package.Standard_Package);
 
       Foreach_Scopes (Node, Add_Decls_For'Access);
    end Enter_Scope;
diff --git a/src/vhdl/simulate/simul-execution.adb b/src/vhdl/simulate/simul-execution.adb
index 3a1c11028..59d91c8ef 100644
--- a/src/vhdl/simulate/simul-execution.adb
+++ b/src/vhdl/simulate/simul-execution.adb
@@ -22,7 +22,7 @@ with System;
 with Grt.Types; use Grt.Types;
 with Flags; use Flags;
 with Errorout; use Errorout;
-with Std_Package;
+with Vhdl.Std_Package;
 with Evaluation;
 with Iirs_Utils; use Iirs_Utils;
 with Simul.Annotations; use Simul.Annotations;
@@ -1321,7 +1321,7 @@ package body Simul.Execution is
                Pos : constant Natural := Get_Enum_Pos (Left);
                Id : Name_Id;
             begin
-               if Base_Type = Std_Package.Character_Type_Definition then
+               if Base_Type = Vhdl.Std_Package.Character_Type_Definition then
                   Result := String_To_Iir_Value ((1 => Character'Val (Pos)));
                else
                   Id := Get_Identifier (Get_Nth_Element (Lits, Pos));
@@ -1418,7 +1418,7 @@ package body Simul.Execution is
                First : Natural;
                Unit : Iir;
             begin
-               Unit := Get_Unit_Chain (Std_Package.Time_Type_Definition);
+               Unit := Get_Unit_Chain (Vhdl.Std_Package.Time_Type_Definition);
                while Unit /= Null_Iir loop
                   exit when Evaluation.Get_Physical_Value (Unit)
                     = Iir_Int64 (Right.I64);
diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb
index 7d6f0e7c7..2d0558308 100644
--- a/src/vhdl/simulate/simul-simulation-main.adb
+++ b/src/vhdl/simulate/simul-simulation-main.adb
@@ -24,7 +24,7 @@ with Errorout; use Errorout;
 with PSL.Nodes;
 with PSL.NFAs;
 with PSL.NFAs.Utils;
-with Std_Package;
+with Vhdl.Std_Package;
 with Trans_Analyzes;
 with Simul.Elaboration; use Simul.Elaboration;
 with Simul.Execution; use Simul.Execution;
@@ -379,7 +379,7 @@ package body Simul.Simulation.Main is
                Res   : Iir_Value_Literal_Acc;
             begin
                Res := Execute_Expression (Instance, E);
-               if Rtype = Std_Package.Boolean_Type_Definition then
+               if Rtype = Vhdl.Std_Package.Boolean_Type_Definition then
                   return Res.B1 = True;
                elsif Rtype = Ieee.Std_Logic_1164.Std_Ulogic_Type then
                   return Res.E8 = 3 or Res.E8 = 7; --  1 or H
diff --git a/src/vhdl/translate/trans-chap12.adb b/src/vhdl/translate/trans-chap12.adb
index 00e071010..f739edb53 100644
--- a/src/vhdl/translate/trans-chap12.adb
+++ b/src/vhdl/translate/trans-chap12.adb
@@ -18,7 +18,7 @@
 
 with Vhdl.Configuration;
 with Errorout; use Errorout;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Iirs_Utils; use Iirs_Utils;
 with Libraries;
 with Flags;
diff --git a/src/vhdl/translate/trans-chap14.adb b/src/vhdl/translate/trans-chap14.adb
index 18c574578..b8e8f71fe 100644
--- a/src/vhdl/translate/trans-chap14.adb
+++ b/src/vhdl/translate/trans-chap14.adb
@@ -17,7 +17,7 @@
 --  02111-1307, USA.
 
 with Evaluation; use Evaluation;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Errorout; use Errorout;
 with Iirs_Utils; use Iirs_Utils;
 with Trans_Decls; use Trans_Decls;
diff --git a/src/vhdl/translate/trans-chap2.adb b/src/vhdl/translate/trans-chap2.adb
index 433d18443..41620bbfd 100644
--- a/src/vhdl/translate/trans-chap2.adb
+++ b/src/vhdl/translate/trans-chap2.adb
@@ -17,7 +17,7 @@
 --  02111-1307, USA.
 
 with Std_Names;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Errorout; use Errorout;
 with Vhdl.Sem_Inst;
 with Nodes_Meta;
diff --git a/src/vhdl/translate/trans-chap4.adb b/src/vhdl/translate/trans-chap4.adb
index 0c44b8af6..01a198563 100644
--- a/src/vhdl/translate/trans-chap4.adb
+++ b/src/vhdl/translate/trans-chap4.adb
@@ -19,7 +19,7 @@
 with Errorout; use Errorout;
 with Files_Map;
 with Iirs_Utils; use Iirs_Utils;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Vhdl.Canon;
 with Translation; use Translation;
 with Trans.Chap2;
diff --git a/src/vhdl/translate/trans-chap7.adb b/src/vhdl/translate/trans-chap7.adb
index 29707e256..a9838e769 100644
--- a/src/vhdl/translate/trans-chap7.adb
+++ b/src/vhdl/translate/trans-chap7.adb
@@ -21,7 +21,7 @@ with Name_Table;
 with Str_Table;
 with Iirs_Utils; use Iirs_Utils;
 with Iir_Chains; use Iir_Chains;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Errorout; use Errorout;
 with Flags; use Flags;
 with Vhdl.Canon;
diff --git a/src/vhdl/translate/trans-chap8.adb b/src/vhdl/translate/trans-chap8.adb
index 815748f35..f78a3d45a 100644
--- a/src/vhdl/translate/trans-chap8.adb
+++ b/src/vhdl/translate/trans-chap8.adb
@@ -22,7 +22,7 @@ with Errorout; use Errorout;
 with Iir_Chains;
 with Vhdl.Canon;
 with Evaluation; use Evaluation;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Iirs_Utils; use Iirs_Utils;
 with Trans.Chap2;
 with Trans.Chap3;
diff --git a/src/vhdl/translate/trans-chap9.adb b/src/vhdl/translate/trans-chap9.adb
index c0b935fa3..0bf153ebf 100644
--- a/src/vhdl/translate/trans-chap9.adb
+++ b/src/vhdl/translate/trans-chap9.adb
@@ -18,7 +18,7 @@
 
 with Iirs_Utils; use Iirs_Utils;
 with Errorout; use Errorout;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Flags;
 with Libraries;
 with Vhdl.Canon;
diff --git a/src/vhdl/translate/translation.adb b/src/vhdl/translate/translation.adb
index 4c5ba5eca..c1cb1e0a4 100644
--- a/src/vhdl/translate/translation.adb
+++ b/src/vhdl/translate/translation.adb
@@ -25,7 +25,7 @@ with Name_Table; -- use Name_Table;
 with Str_Table;
 with Files_Map;
 with Iirs_Utils; use Iirs_Utils;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Vhdl.Sem_Specs;
 with Libraries;
 with Std_Names;
diff --git a/src/vhdl/vhdl-configuration.adb b/src/vhdl/vhdl-configuration.adb
index 8d06a3a73..0c688a083 100644
--- a/src/vhdl/vhdl-configuration.adb
+++ b/src/vhdl/vhdl-configuration.adb
@@ -18,7 +18,7 @@
 
 with Libraries;
 with Errorout; use Errorout;
-with Std_Package;
+with Vhdl.Std_Package;
 with Name_Table; use Name_Table;
 with Flags;
 with Iirs_Utils; use Iirs_Utils;
@@ -675,8 +675,8 @@ package body Vhdl.Configuration is
       end case;
 
       --  Exclude std.standard
-      Set_Configuration_Mark_Flag (Std_Package.Std_Standard_Unit, True);
-      Set_Configuration_Done_Flag (Std_Package.Std_Standard_Unit, True);
+      Set_Configuration_Mark_Flag (Vhdl.Std_Package.Std_Standard_Unit, True);
+      Set_Configuration_Done_Flag (Vhdl.Std_Package.Std_Standard_Unit, True);
 
       Add_Design_Unit (Top, Null_Iir);
       return Top;
diff --git a/src/vhdl/vhdl-disp_vhdl.adb b/src/vhdl/vhdl-disp_vhdl.adb
index f905a171a..acf7f0c5f 100644
--- a/src/vhdl/vhdl-disp_vhdl.adb
+++ b/src/vhdl/vhdl-disp_vhdl.adb
@@ -21,7 +21,7 @@
 --  input file.  If parenthesis are kept by the parser, the only differences
 --  are comments and layout.
 with GNAT.OS_Lib;
-with Std_Package;
+with Vhdl.Std_Package;
 with Flags; use Flags;
 with Errorout; use Errorout;
 with Iirs_Utils; use Iirs_Utils;
@@ -442,10 +442,10 @@ package body Vhdl.Disp_Vhdl is
       Base_Type: Iir_Integer_Type_Definition;
       Decl: Iir;
    begin
-      if Def /= Std_Package.Universal_Integer_Subtype_Definition then
+      if Def /= Vhdl.Std_Package.Universal_Integer_Subtype_Definition then
          Base_Type := Get_Base_Type (Def);
          Decl := Get_Type_Declarator (Base_Type);
-         if Base_Type /= Std_Package.Universal_Integer_Subtype_Definition
+         if Base_Type /= Vhdl.Std_Package.Universal_Integer_Subtype_Definition
            and then Def /= Decl
          then
             Disp_Name_Of (Decl);
@@ -464,10 +464,10 @@ package body Vhdl.Disp_Vhdl is
       Base_Type: Iir_Floating_Type_Definition;
       Decl: Iir;
    begin
-      if Def /= Std_Package.Universal_Real_Subtype_Definition then
+      if Def /= Vhdl.Std_Package.Universal_Real_Subtype_Definition then
          Base_Type := Get_Base_Type (Def);
          Decl := Get_Type_Declarator (Base_Type);
-         if Base_Type /= Std_Package.Universal_Real_Subtype_Definition
+         if Base_Type /= Vhdl.Std_Package.Universal_Real_Subtype_Definition
            and then Def /= Decl
          then
             Disp_Name_Of (Decl);
@@ -2683,7 +2683,7 @@ package body Vhdl.Disp_Vhdl is
       Put (Name);
       Param := Get_Parameter (Expr);
       if Param /= Null_Iir
-        and then Param /= Std_Package.Universal_Integer_One
+        and then Param /= Vhdl.Std_Package.Universal_Integer_One
       then
          Put (" (");
          Disp_Expression (Param);
diff --git a/src/vhdl/vhdl-sem.adb b/src/vhdl/vhdl-sem.adb
index b1875bc1e..878713ce6 100644
--- a/src/vhdl/vhdl-sem.adb
+++ b/src/vhdl/vhdl-sem.adb
@@ -16,7 +16,7 @@
 --  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 --  02111-1307, USA.
 with Errorout; use Errorout;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Ieee.Std_Logic_1164;
 with Libraries;
 with Std_Names;
diff --git a/src/vhdl/vhdl-sem_assocs.adb b/src/vhdl/vhdl-sem_assocs.adb
index 146b582bc..403f720ef 100644
--- a/src/vhdl/vhdl-sem_assocs.adb
+++ b/src/vhdl/vhdl-sem_assocs.adb
@@ -25,7 +25,7 @@ with Std_Names;
 with Vhdl.Sem_Names; use Vhdl.Sem_Names;
 with Vhdl.Sem_Types;
 with Vhdl.Sem_Decls;
-with Std_Package;
+with Vhdl.Std_Package;
 with Vhdl.Sem_Scopes;
 with Iir_Chains; use Iir_Chains;
 with Xrefs;
@@ -1499,7 +1499,7 @@ package body Vhdl.Sem_Assocs is
          end if;
          --  That returns a boolean.
          if (Get_Base_Type (Get_Return_Type (Decl))
-               /= Std_Package.Boolean_Type_Definition)
+               /= Vhdl.Std_Package.Boolean_Type_Definition)
          then
             return False;
          end if;
diff --git a/src/vhdl/vhdl-sem_decls.adb b/src/vhdl/vhdl-sem_decls.adb
index f8e380c95..f67fcd96c 100644
--- a/src/vhdl/vhdl-sem_decls.adb
+++ b/src/vhdl/vhdl-sem_decls.adb
@@ -20,7 +20,7 @@ with Types; use Types;
 with Std_Names;
 with Vhdl.Tokens;
 with Flags; use Flags;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Evaluation; use Evaluation;
 with Iirs_Utils; use Iirs_Utils;
 with Vhdl.Sem; use Vhdl.Sem;
diff --git a/src/vhdl/vhdl-sem_expr.adb b/src/vhdl/vhdl-sem_expr.adb
index 9ac79c601..cd9f9a2d5 100644
--- a/src/vhdl/vhdl-sem_expr.adb
+++ b/src/vhdl/vhdl-sem_expr.adb
@@ -17,7 +17,7 @@
 --  02111-1307, USA.
 
 with Grt.Algos;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Errorout; use Errorout;
 with Flags; use Flags;
 with Vhdl.Sem_Scopes; use Vhdl.Sem_Scopes;
diff --git a/src/vhdl/vhdl-sem_names.adb b/src/vhdl/vhdl-sem_names.adb
index d72af8c28..3f49ae99a 100644
--- a/src/vhdl/vhdl-sem_names.adb
+++ b/src/vhdl/vhdl-sem_names.adb
@@ -20,7 +20,7 @@ with Iirs_Utils; use Iirs_Utils;
 with Errorout; use Errorout;
 with Flags; use Flags;
 with Name_Table;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Types; use Types;
 with Iir_Chains; use Iir_Chains;
 with Std_Names;
diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb
index 41a2e74d9..a528da0be 100644
--- a/src/vhdl/vhdl-sem_psl.adb
+++ b/src/vhdl/vhdl-sem_psl.adb
@@ -28,7 +28,7 @@ with Vhdl.Sem_Names;
 with Std_Names;
 with Iirs_Utils; use Iirs_Utils;
 with Evaluation; use Evaluation;
-with Std_Package;
+with Vhdl.Std_Package;
 with Ieee.Std_Logic_1164;
 with Errorout; use Errorout;
 with Xrefs; use Xrefs;
@@ -46,8 +46,8 @@ package body Vhdl.Sem_Psl is
          return False;
       end if;
       Btype := Get_Base_Type (Atype);
-      return Btype = Std_Package.Boolean_Type_Definition
-        or else Btype = Std_Package.Bit_Type_Definition
+      return Btype = Vhdl.Std_Package.Boolean_Type_Definition
+        or else Btype = Vhdl.Std_Package.Bit_Type_Definition
         or else Btype = Ieee.Std_Logic_1164.Std_Ulogic_Type;
    end Is_Psl_Bool_Type;
 
@@ -544,7 +544,7 @@ package body Vhdl.Sem_Psl is
 
       --  Endpoints are considered as an HDL declaration and must have a
       --  type.
-      Set_Type (Stmt, Std_Package.Boolean_Type_Definition);
+      Set_Type (Stmt, Vhdl.Std_Package.Boolean_Type_Definition);
       Set_Expr_Staticness (Stmt, None);
 
       Set_Visible_Flag (Stmt, True);
@@ -600,7 +600,7 @@ package body Vhdl.Sem_Psl is
       if Get_Type (Cond) = Null_Iir then
          Cond := Sem_Expr.Sem_Condition (Cond);
       elsif Get_Base_Type (Get_Type (Cond))
-        /= Std_Package.Boolean_Type_Definition
+        /= Vhdl.Std_Package.Boolean_Type_Definition
       then
          Cond := Sem_Expr.Insert_Condition_Operator (Cond);
       end if;
diff --git a/src/vhdl/vhdl-sem_specs.adb b/src/vhdl/vhdl-sem_specs.adb
index bd21e7e47..3ed4ec571 100644
--- a/src/vhdl/vhdl-sem_specs.adb
+++ b/src/vhdl/vhdl-sem_specs.adb
@@ -19,7 +19,7 @@ with Iirs_Utils; use Iirs_Utils;
 with Vhdl.Sem_Expr; use Vhdl.Sem_Expr;
 with Vhdl.Sem_Names; use Vhdl.Sem_Names;
 with Evaluation; use Evaluation;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Errorout; use Errorout;
 with Vhdl.Sem; use Vhdl.Sem;
 with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
diff --git a/src/vhdl/vhdl-sem_stmts.adb b/src/vhdl/vhdl-sem_stmts.adb
index 9a616896a..c79f69496 100644
--- a/src/vhdl/vhdl-sem_stmts.adb
+++ b/src/vhdl/vhdl-sem_stmts.adb
@@ -19,7 +19,7 @@ with Errorout; use Errorout;
 with Types; use Types;
 with Flags; use Flags;
 with Vhdl.Sem_Specs; use Vhdl.Sem_Specs;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Vhdl.Sem; use Vhdl.Sem;
 with Vhdl.Sem_Decls; use Vhdl.Sem_Decls;
 with Vhdl.Sem_Expr; use Vhdl.Sem_Expr;
diff --git a/src/vhdl/vhdl-sem_types.adb b/src/vhdl/vhdl-sem_types.adb
index 20651c000..f56ba309b 100644
--- a/src/vhdl/vhdl-sem_types.adb
+++ b/src/vhdl/vhdl-sem_types.adb
@@ -29,7 +29,7 @@ with Vhdl.Sem_Inst;
 with Name_Table;
 with Std_Names;
 with Iirs_Utils; use Iirs_Utils;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 with Ieee.Std_Logic_1164;
 with Xrefs; use Xrefs;
 
diff --git a/src/vhdl/vhdl-sem_utils.adb b/src/vhdl/vhdl-sem_utils.adb
index 06dfa5a50..a82628dde 100644
--- a/src/vhdl/vhdl-sem_utils.adb
+++ b/src/vhdl/vhdl-sem_utils.adb
@@ -23,7 +23,7 @@ with Iirs_Utils; use Iirs_Utils;
 with Iir_Chains; use Iir_Chains;
 with Ieee.Std_Logic_1164;
 with Std_Names;
-with Std_Package; use Std_Package;
+with Vhdl.Std_Package; use Vhdl.Std_Package;
 
 package body Vhdl.Sem_Utils is
    procedure Compute_Subprogram_Hash (Subprg : Iir)
diff --git a/src/vhdl/std_package.adb b/src/vhdl/vhdl-std_package.adb
index 5dd659d6a..78a614afd 100644
--- a/src/vhdl/std_package.adb
+++ b/src/vhdl/vhdl-std_package.adb
@@ -25,7 +25,7 @@ with Iirs_Utils;
 with Vhdl.Sem_Utils;
 with Iir_Chains;
 
-package body Std_Package is
+package body Vhdl.Std_Package is
    type Bound_Array is array (Boolean) of Iir_Int64;
    Low_Bound : constant Bound_Array := (False => -(2 ** 31),
                                         True => -(2 ** 63));
@@ -1360,4 +1360,4 @@ package body Std_Package is
       end if;
       return '?';
    end Get_Minimal_Time_Resolution;
-end Std_Package;
+end Vhdl.Std_Package;
diff --git a/src/vhdl/std_package.ads b/src/vhdl/vhdl-std_package.ads
index f8830ae2e..f20364e10 100644
--- a/src/vhdl/std_package.ads
+++ b/src/vhdl/vhdl-std_package.ads
@@ -19,7 +19,7 @@
 with Types; use Types;
 with Iirs; use Iirs;
 
-package Std_Package is
+package Vhdl.Std_Package is
 
    --  This is a special node, not really declared in the STANDARD package,
    --  used to mark a node as erroneous.
@@ -199,4 +199,4 @@ private
      := 5;
    Convertible_Real_Type_Definition : constant Iir_Floating_Type_Definition
      := 6;
-end Std_Package;
+end Vhdl.Std_Package;
diff --git a/src/vhdl/xrefs.adb b/src/vhdl/xrefs.adb
index d04a7d135..8b66339e2 100644
--- a/src/vhdl/xrefs.adb
+++ b/src/vhdl/xrefs.adb
@@ -18,7 +18,7 @@
 with Tables;
 with GNAT.Heap_Sort_A;
 with Flags;
-with Std_Package;
+with Vhdl.Std_Package;
 with Errorout; use Errorout;
 with Nodes;
 
@@ -127,7 +127,7 @@ package body Xrefs is
             declare
                Res : constant Iir := Get_Named_Entity (Name);
             begin
-               if Res = Std_Package.Error_Mark then
+               if Res = Vhdl.Std_Package.Error_Mark then
                   return;
                end if;
                Add_Xref (Get_Location (Name), Res, Xref_Ref);