From 344ca60dd3b9cc8547951a5573b1bb209b3e7b5b Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 5 Dec 2017 05:19:27 +0100
Subject: simul: psl default clock, unaffected waveform.

---
 src/vhdl/simulate/simul-annotations.adb | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/vhdl/simulate/simul-annotations.adb')

diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/simulate/simul-annotations.adb
index fb03495e4..4c6e6e80b 100644
--- a/src/vhdl/simulate/simul-annotations.adb
+++ b/src/vhdl/simulate/simul-annotations.adb
@@ -717,6 +717,9 @@ package body Simul.Annotations is
          when Iir_Kind_Nature_Declaration =>
             null;
 
+         when Iir_Kind_Psl_Default_Clock =>
+            null;
+
          when others =>
             Error_Kind ("annotate_declaration", Decl);
       end case;
-- 
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