From e807a08d64c7dbf18edd4a3a99fd1f7cbd655055 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 10 Oct 2022 07:44:25 +0200 Subject: simul-vhdl_debug: handle state before elaboration --- src/simul/simul-vhdl_debug.adb | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/simul') diff --git a/src/simul/simul-vhdl_debug.adb b/src/simul/simul-vhdl_debug.adb index 8edf963d8..8eb2c1cab 100644 --- a/src/simul/simul-vhdl_debug.adb +++ b/src/simul/simul-vhdl_debug.adb @@ -216,6 +216,10 @@ package body Simul.Vhdl_Debug is Sig : Ghdl_Signal_Ptr; begin Sig := Simul.Vhdl_Simul.Read_Sig (S.Mem); + if Sig = null then + Put_Line ("*not yet elaborated*"); + return; + end if; Put_Addr (Sig.all'Address); Put (' '); Grt.Disp_Signals.Disp_Single_Signal_Attributes (Sig); @@ -333,6 +337,10 @@ package body Simul.Vhdl_Debug is Ctxt : Rti_Context; begin Sig := Simul.Vhdl_Simul.Read_Sig (S.Mem); + if Sig = null then + Put_Line ("*not yet elaborated*"); + return; + end if; Put_Addr (Sig.all'Address); Put (' '); Ev := Sig.Event_List; -- cgit v1.2.3