From 1e5f96642bbf470934f245c98908337f75abb35a Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 3 Jan 2023 13:53:37 +0100 Subject: synth: introduce type_array_unbounded --- src/simul/simul-vhdl_debug.adb | 1 + src/simul/simul-vhdl_elab.adb | 1 + src/simul/simul-vhdl_simul.adb | 2 ++ 3 files changed, 4 insertions(+) (limited to 'src/simul') diff --git a/src/simul/simul-vhdl_debug.adb b/src/simul/simul-vhdl_debug.adb index 8eb2c1cab..fe49e2292 100644 --- a/src/simul/simul-vhdl_debug.adb +++ b/src/simul/simul-vhdl_debug.adb @@ -315,6 +315,7 @@ package body Simul.Vhdl_Debug is end; when Type_Unbounded_Vector | Type_Unbounded_Record + | Type_Array_Unbounded | Type_Unbounded_Array | Type_Slice | Type_Protected diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 229c75c77..8480432a6 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -123,6 +123,7 @@ package body Simul.Vhdl_Elab is when Type_Slice | Type_Access + | Type_Array_Unbounded | Type_Unbounded_Vector | Type_Unbounded_Array | Type_Unbounded_Record diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 354ca062f..37fd14d69 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2576,6 +2576,7 @@ package body Simul.Vhdl_Simul is when Type_Slice | Type_Access + | Type_Array_Unbounded | Type_Unbounded_Vector | Type_Unbounded_Array | Type_Unbounded_Record @@ -2739,6 +2740,7 @@ package body Simul.Vhdl_Simul is when Type_Slice | Type_Access + | Type_Array_Unbounded | Type_Unbounded_Vector | Type_Unbounded_Array | Type_Unbounded_Record -- cgit v1.2.3