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| author | 1138-4EB <1138-4EB@users.noreply.github.com> | 2017-12-09 17:34:58 +0100 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2017-12-10 12:02:05 +0100 |
| commit | 8e06c39ed8311aeb36696d9f964550407e1c556e (patch) | |
| tree | 5c511441a8c0b2a9bb2f5732dd4284ed725ad24a /doc/using/QuickStartGuide.rst | |
| parent | 08eb2bfc7144e7698cf570478d6a4e3e81aaf31a (diff) | |
| download | ghdl-8e06c39ed8311aeb36696d9f964550407e1c556e.tar.gz ghdl-8e06c39ed8311aeb36696d9f964550407e1c556e.tar.bz2 ghdl-8e06c39ed8311aeb36696d9f964550407e1c556e.zip | |
clean todos
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| -rw-r--r-- | doc/using/QuickStartGuide.rst | 10 |
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diff --git a/doc/using/QuickStartGuide.rst b/doc/using/QuickStartGuide.rst index b390b382e..a1afa00b2 100644 --- a/doc/using/QuickStartGuide.rst +++ b/doc/using/QuickStartGuide.rst @@ -216,13 +216,3 @@ Unless you are only studying VHDL, you will work with larger designs than the on * Remove the :file:`work/` directory: ``rm -rf work``. Only the executable is kept. If you want to rebuild the design, create the :file:`work/` directory, import the sources, and make the design. .. WARNING:: Sometimes, a design does not fully follow the VHDL standards. For example it uses the badly engineered ``std_logic_unsigned`` package. GHDL supports this VHDL dialect through some options: ``--ieee=synopsys -fexplicit``. See section ':ref:`IEEE_library_pitfalls`', for more details. - -Further examples -======================= - -.. TODO:: - - * Add references to examples/tutorials with GHDL. - * Shall `René Doß <https://mail.gna.org/public/ghdl-discuss/2017-01/msg00000.html>` want to contribute adapting his article to RST? - * https://github.com/Obijuan/open-fpga-verilog-tutorial/wiki ->>>>>>> doc/changelog renamed to doc/appendix |