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diff --git a/COPYING b/COPYING new file mode 100644 index 000000000..d60c31a97 --- /dev/null +++ b/COPYING @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Library General Public License instead.) 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See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + <signature of Ty Coon>, 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. @@ -1,14 +1,17 @@ -**v0.34-dev** +**0.35-dev** (XXXX-XX-XX) +* Assert and report messages are sent to stdout (#394) + +**0.34** (2017-08-15) - Display stack backtraces on errors or assert failures - Compile scripts for vendor libraries (Xilinx, Altera, osvvm, vunit) - Use SSE2 for mcode backend -- Mode backend ported to `x86_64` +- mcode backend ported to `x86_64` - Support cocotb [potentialventures/cocotb](https://github.com/potentialventures/cocotb) - Main repository is now on github: [github.com/tgingold/ghdl](https://github.com/tgingold/ghdl) - Docs available on rtd: [ghdl.readthedocks.org](https://ghdl.readthedocs.org/en/latest/) - Speed improved. - New option `--psl-report`, to report status of PSL assert and cover. -- VHDL2008: support nested packages +- VHDL2008: support nested package **v0.33** (2015-10-04) - Improve support of VHDL2008 @@ -95,7 +98,7 @@ Never released, swith to Dunoon Edition. - `math_real` now works under windows. - documentation updated for windows. - filename/line number displayed for range error during signal update. -- bug fix: +- bug fix: - ieee math libraries available when `--ieee=synopsys`. - `'image` in package bodies. - scan of fp literals. @@ -31,21 +31,6 @@ GHDL is free software: Periodically (not regularly), several binary distributions are made available through the [releases](https://github.com/tgingold/ghdl/releases) tab. If you can't find the one matching the platform and versions you need, you can build it yourself! -### Docker containers - -If you don't want to install the dependencies in your own filesystem, [Docker](https://www.docker.com/) containers can be used. You can have the latest version compiled and automatically placed in your current path with: - -``` -wget "https://raw.githubusercontent.com/tgingold/ghdl/master/dist/linux/docker-buildtest.sh" -chmod +x docker-buildtest.sh -./docker-buildtest.sh -i "ghdl/ghdl-tools:fedora-llvm-cmp" -b "mcode" -f "ghdl-mcode.tgz" -g -``` - -See '[Docker](http://ghdl.readthedocs.io/en/latest/getting/Docker.html)' for a list of available images and compiler options. You will also find images with GHDL installed already, so that you can directly start using it without caring about the platform! - -*If you are new to docker, keep in mind that it's not significantly different from the traditional way. Exactly the same commands are executed, but it's done in a box similar to a virtual machine.* ->>>>>>> README.md, index, WhatIsVHDL, WhatIsGHDL ready for review. - ### Building GHDL In order to follow the traditional way to `configure` and `make`, you need the GNU Ada compiler, GNAT GPL, 2014 (or later) for x86 (32 or 64 bits). GNAT GPL can be downloaded anonymously from [libre.adacore.com](http://libre.adacore.com/tools/gnat-gpl-edition/). Then, untar and run the *doinstall* script. @@ -82,4 +67,4 @@ Furthermore, each supported compiler has its pros and cons. Here is a short comp LLVM has the same pros/cons as GCC, but it is easier to build. However, coverage (`gcov`) is unique to GCC. -You can find specific instructions for each of the options in '[Building](http://ghdl.readthedocs.io/en/latest/building/index.html)'. +You can find specific instructions for each of the options in '[Building](http://ghdl.readthedocs.io/en/latest/building/Building.html)'. diff --git a/doc/appendix/2014/index.rst b/doc/appendix/2014/index.rst deleted file mode 100644 index 5822e67e7..000000000 --- a/doc/appendix/2014/index.rst +++ /dev/null @@ -1,20 +0,0 @@ -.. _CHANGE:2014: - -2014 -#### - -.. contents:: Content of this page - :local: - -.. only:: html - - .. toctree:: - - v0.30 <v0.30> - - -.. only:: latex - - .. toctree:: - - v0.30 <v0.30> diff --git a/doc/appendix/2014/v0.30.rst b/doc/appendix/2014/v0.30.rst deleted file mode 100644 index 87ebef22f..000000000 --- a/doc/appendix/2014/v0.30.rst +++ /dev/null @@ -1,4 +0,0 @@ -.. _CHANGE:v0.30: - -New in 0.30 (xx.yy.2014) -================================================================================================================================================================ diff --git a/doc/appendix/2015/index.rst b/doc/appendix/2015/index.rst deleted file mode 100644 index 3a3dc1ed5..000000000 --- a/doc/appendix/2015/index.rst +++ /dev/null @@ -1,20 +0,0 @@ -.. _CHANGE:2015: - -2015 -#### - -.. contents:: Content of this page - :local: - -.. only:: html - - .. toctree:: - - v0.31 <v0.31> - - -.. only:: latex - - .. toctree:: - - v0.31 <v0.31> diff --git a/doc/appendix/2015/v0.31.rst b/doc/appendix/2015/v0.31.rst deleted file mode 100644 index 71bab8013..000000000 --- a/doc/appendix/2015/v0.31.rst +++ /dev/null @@ -1,4 +0,0 @@ -.. _CHANGE:v0.31: - -New in 0.31 (xx.yy.2015) -================================================================================================================================================================ diff --git a/doc/appendix/2016/index.rst b/doc/appendix/2016/index.rst deleted file mode 100644 index 340fb915d..000000000 --- a/doc/appendix/2016/index.rst +++ /dev/null @@ -1,22 +0,0 @@ -.. _CHANGE:2016: - -2016 -#### - -.. contents:: Content of this page - :local: - -.. only:: html - - .. toctree:: - - v0.33 <v0.33> - v0.32 <v0.32> - - -.. only:: latex - - .. toctree:: - - v0.32 <v0.32> - v0.33 <v0.33> diff --git a/doc/appendix/2016/v0.32.rst b/doc/appendix/2016/v0.32.rst deleted file mode 100644 index ae6ff7a12..000000000 --- a/doc/appendix/2016/v0.32.rst +++ /dev/null @@ -1,4 +0,0 @@ -.. _CHANGE:v0.32: - -New in 0.32 (xx.yy.2016) -================================================================================================================================================================ diff --git a/doc/appendix/2016/v0.33.rst b/doc/appendix/2016/v0.33.rst deleted file mode 100644 index 676390771..000000000 --- a/doc/appendix/2016/v0.33.rst +++ /dev/null @@ -1,4 +0,0 @@ -.. _CHANGE:v0.33: - -New in 0.33 (xx.yy.2016) -================================================================================================================================================================ diff --git a/doc/appendix/2017/index.rst b/doc/appendix/2017/index.rst deleted file mode 100644 index fa4ed0f1c..000000000 --- a/doc/appendix/2017/index.rst +++ /dev/null @@ -1,20 +0,0 @@ -.. _CHANGE:2017: - -2017 -#### - -.. contents:: Content of this page - :local: - -.. only:: html - - .. toctree:: - - v0.34 <v0.34> - - -.. only:: latex - - .. toctree:: - - v0.34 <v0.34> diff --git a/doc/appendix/2017/v0.34.rst b/doc/appendix/2017/v0.34.rst deleted file mode 100644 index 874a36728..000000000 --- a/doc/appendix/2017/v0.34.rst +++ /dev/null @@ -1,4 +0,0 @@ -.. _CHANGE:v0.34: - -New in 0.34 (xx.yy.2017) -================================================================================================================================================================ diff --git a/doc/appendix/Changelog.rst b/doc/appendix/Changelog.rst deleted file mode 100644 index 43367c456..000000000 --- a/doc/appendix/Changelog.rst +++ /dev/null @@ -1,22 +0,0 @@ -.. _CHANGE: - -Change Log -########## - -.. only:: html - - .. toctree:: - - 2017/index - 2016/index - 2015/index - 2014/index - -.. only:: latex - - .. toctree:: - - 2014/index - 2015/index - 2016/index - 2017/index diff --git a/doc/appendix/Roadmap.rst b/doc/appendix/Roadmap.rst index 0d48c6c5c..7854e3b68 100644 --- a/doc/appendix/Roadmap.rst +++ b/doc/appendix/Roadmap.rst @@ -12,35 +12,5 @@ I have several axes for `GHDL` improvements: * Graphical tools (to see waves and to debug) * Style checks * VITAL acceleration - -TODOs -===== - -* RTD builds fail if EPUB is activated. -* Convert VendorPrimitives Markdown to RST -* SVG images are not shown in the PDF. That's because LaTeX is used. Can any package be added to allow so? -* Create a fancy Shield with a ZIP/TGZ icon, that points to the source code zip and tar.gz/tgz: - - * https://github.com/tgingold/ghdl/archive/2017-03-01.zip - * https://github.com/tgingold/ghdl/archive/2017-03-01.tar.gz - -* The URL of some sections does not match the position in the hierarchy shown in the side menu. We have several options: - - * Leave it as it is now. - * Create a new chapter in the side menu, named 'Building GHDL' and move 'Builing' and 'Precompile Vendor Primitives' there. - * Move 'Releases' to ch Introduction, renamed to 'Getting'. And keep 'Building', 'Vendor...' and 'Docker' in the same chapter, renamed to 'Building'. - - We are going to write more content first, and see how much we get. We'll reorder afterwards. - - [@Paebbels] I have no problem if a chapter has different URLs for sections. Users use either the web-gui / navigation bar or remember an url in the browser history, the will not see the discrepancy because the use only one access way. - -Options shown in the command line help, but not found in the doc: - -* ``--syn-binding use synthesis default binding rule`` - -* VPI Commands - - * ``--vpi=FILENAME load VPI module`` - * ``--vpi-trace[=FILE] trace vpi calls to FILE`` -.. todolist::
\ No newline at end of file +.. todolist:: diff --git a/doc/building/Building.rst b/doc/building/Building.rst index a8d0e6908..f8f939c57 100644 --- a/doc/building/Building.rst +++ b/doc/building/Building.rst @@ -7,20 +7,12 @@ Building GHDL from Sources GHDL can be downloaded as a `zip-file <https://github.com/tgingold/ghdl/archive/master.zip>`_ (latest 'master' branch) or cloned with ``git clone`` from GitHub. GitHub -offers HTTPS and SSH as transfer protocols. See the :ref:`Download <GETTING:Download>` +offers HTTPS and SSH as transfer protocols. See the :ref:`RELEASE:Sources` page for further details. The installation directory is referred to as ``GHDLRoot``. -+----------+-----------------------------------------------------------+ -| Protocol | Git Clone Command | -+==========+===========================================================+ -| HTTPS | ``git clone https://github.com/tgingold/ghdl.git ghdl`` | -+----------+-----------------------------------------------------------+ -| SSH | ``git clone ssh://git@github.com:tgingold/ghdl.git ghdl`` | -+----------+-----------------------------------------------------------+ - .. rubric:: Available back-ends -GHDL currently supports three supported different back-ends (code generators): +GHDL currently supports three different back-ends (code generators): * mcode - built-in x86(or x86_64) code generator, * `GCC - Gnu Compiler Collection <http://gcc.gnu.org/>`_, and @@ -43,10 +35,10 @@ Here is a short comparison, so that you can choose the one you want to use: | | * Generated code can be debugged (with ``-g``) | * Analysis can take time (particularly for large units) | | | * Ported to many platforms (x86, x86_64, PowerPC, SPARC) | * Code coverage collection (``gcov``) is unique to GCC | +----------------------------+----------------------------------------------------------------------------+---------------------------------------------------------+ - + .. toctree:: :hidden: - + Directories With mcode Backend <mcode/index> With LLVM Backend <llvm/index> @@ -69,14 +61,3 @@ created. (32 or 64 bits). `GNAT GPL` can be downloaded anonymously from `libre.adacore.com <http://libre.adacore.com/tools/gnat-gpl-edition/>`_. Then, untar and run the doinstall script. Alternatively, most GNU/Linux provide a package named ``gcc-ada`` or ``gcc-gnat``. - -.. TODO:: - - * @1138 Backtraces optional -patchable- - * Very briefly, why is mcode faster for analysis and GCC/LLVM for simulation? - * The only other dependency is zlib (On ubuntu/debian, install zlib1g-dev). - * From :ghdlsharp:`279`: - * GCC: GHDL generates an intermediate representation for GCC, which creates an executable. So GHDL acts a a new language frontend like C for the GCC and uses the existing backend to generated e.g. x86(-64) binary code. - * LLVM: GHDL generates instructions for the LLVM abstract register machine, which then generates x86(-64) instructions for the host system. - * mcode: GHDL generates the x86(-64) instructions in memory and executes the model. - * gcc is currently only supported on Linux, because you need to compile a complete GCC from zero and add GHDL as a frontend into the GCC. Compiling the complete GCC suite plus GHDL takes a lot of time. I think it's not possible to finish the compile task in the bounds of a Travis-CI run. diff --git a/doc/building/Directories.rst b/doc/building/Directories.rst index 5a121ba55..36c0f2d9e 100644 --- a/doc/building/Directories.rst +++ b/doc/building/Directories.rst @@ -16,21 +16,21 @@ Directory Structure computer. These are located in ``libraries/vendor``. See Vendor Primitives <VendorPrimitives.html> for information on how to use them. - + * ``dist``: scripts and auxiliar files to build GHDL in different environments: - + * ``gcc``: header and configuration files to build GHDL with GCC (all the platforms). * ``linux``: build and test script written in shell, and other auxiliary files used to i) launch docker containers and ii) automate multiple builds in `Travis CI <https://travis-ci.org/>`_. - + * ``windows``: - + * ``mcode``: - * ``appveyor``: - + * ``appveyor``: + * ``doc``: `Markdown` and `reStructuredText` sources and auxiliary files to build the documentation with `Sphinx <http://www.sphinx-doc.org>`_. Indeed, `Read the docs <http://readthedocs.org>`_ (RTD) is used to automatically build @@ -48,12 +48,3 @@ Directory Structure (GNAT project file). * Text files: ``COPYING.md``, ``NEWS.md`` and ``README.md``. - - -.. TODO:: - - - [@1138-4EB|@Paebbels] Replace link to VendorPrimitives, when the file is translated from md to rst. - - - [@Paebbels] Add brief description of how the content in dist/windows is ordered. From :ghdlsharp:`279`: - - The content in dist/appveyor is for the AppVeyor flow. AppVeyor is a continuous integration service like Travis-CI, but is offers a Windows Server 2012 R2 machine. The AppVeyor flow has more scripts than the Travis-CI flow, so we put them into a separate directory. - - The code in dist/windows/mcode is special code needed to build mcode in windows. mcode is supported on Linux (32/64-bit) and Windows (32-bit). diff --git a/doc/building/TestSuites.rst b/doc/building/TestSuites.rst deleted file mode 100644 index 609e98755..000000000 --- a/doc/building/TestSuites.rst +++ /dev/null @@ -1,11 +0,0 @@ -.. _BUILD:testsuites: - -Test Suites -=========== - -.. TODO:: - - * @1138 explain that there are two (maybe three with vhdl08 tests) - * ``--expect-failure invert exit status`` - * ``--has-feature=X test presence of feature X`` - * ``--list-features display the list of features`` diff --git a/doc/building/gcc/GNULinux-GNAT.rst b/doc/building/gcc/GNULinux-GNAT.rst index e35768fdb..3733d763f 100644 --- a/doc/building/gcc/GNULinux-GNAT.rst +++ b/doc/building/gcc/GNULinux-GNAT.rst @@ -17,42 +17,10 @@ On Linux, GHDL is configured by ``configure`` and build by ``make``. .. rubric:: Example: .. code-block:: Bash - + cd <ghdl> mkdir build cd build ../configure --prefix=PREFIX make sudo make install - -.. TODO:: - - First configure GHDL, specify GCC source dir and :samp:`prefix` (replace :samp:`/usr/local` with your desired installation directory):: - - ./configure --with-gcc=/path/to/gcc/source/dir --prefix=/usr/local - - - Then, invoke :samp:`make` to copy GHDL sources in the source dir:: - - make copy-sources - - .. HINT:: There are some dependencies for building GCC (:samp:`gmp`, :samp:`mpfr` and :samp:`mpc`). If you have not them installed on your system, you can either build them manually or use the :samp:`download_prerequisite` script provided in the GCC source tree (recommended): :samp:`cd /path/to/gcc/source/dir && ./contrib/download_prerequisites` - - - Then, configure GCC. The list of :samp:`--disable` configure options can be adjusted to your needs. GHDL does not require all these optional libraries and disabling them will speed-up the build:: - - ../gcc-4.9.3/configure --prefix=/usr/local --enable-languages=c,vhdl \ - --disable-bootstrap --disable-lto --disable-multilib --disable-libssp \ - --disable-libgomp --disable-libquadmath ``. - - .. HINT:: Note that the prefix directory must be the same as the one used to configure GHDL. If you have manually built :samp:`gmp`/:samp:`mpfr`/:samp:`mpc` (without using the script in :samp:`contrib`) and if you have installed them in a non-standard directory, you may need to add :samp:`--with-gmp=GMP_INSTALL_DIR`. - - - Then, build and install GCC:: - - make -j2 && make install - - .. HINT:: If you don't want to install :samp:`makeinfo`, do :samp:`make install MAKEINFO=false` instead. - - - Last, build and install GHDL libraries:: - - cd /path/to/ghdl/source/dir - make ghdllib - make install -
\ No newline at end of file diff --git a/doc/building/gcc/index.rst b/doc/building/gcc/index.rst index 377392681..c17775e23 100644 --- a/doc/building/gcc/index.rst +++ b/doc/building/gcc/index.rst @@ -20,36 +20,3 @@ GCC Backend GNU/Linux with GCC/GNAT <GNULinux-GNAT> Windows with GCC/GNAT (MinGW) <Windows-MinGW-GNAT> - - - -.. TODO:: - - - You need to download and untar the sources of GCC version 4.9.x, 5.x or 6.x - - gcc object dir - - Notes for developpers developping with the GCC backend: once GCC (with GHDL) has been built once, it is possible to work on the GHDL source tree without copying it in the GCC tree. Commands are:: - - $ make ghdl1-gcc # Build the compiler - $ make ghdl_gcc # Build the driver - $ make libs.vhdl.local_gcc # Compile the vhdl libraries - $ make grt-all # Build the GHDL runtime - $ make grt.links # Locally install the GHDL runtime - - -.. TODO: - - Note for ppc64 (and AIX ?) platform: the object file format contains an identifier for the source language. Because gcc doesn't know about the VHDL, gcc crashes very early. This could be fixed with a very simple change in gcc/config/rs6000/rs6000.c, function rs6000_output_function_epilogue (as of gcc 4.8): - - .. CODE:: C - - else if (! strcmp (language_string, "GNU Objective-C")) - i = 14; - else - - gcc_unreachable (); - + i = 0; - fprintf (file, "%d,", i); - - /* 8 single bit fields: global linkage (not set for C extern linkage, - - Install file for the binary distribution of GHDL. The binary are installed in /usr/local directory. You cannot change this default location, unless you set links. You must be root to install this distribution. To install ghdl: `tar -C / -jxvf @TARFILE@.tar.bz2`. Note: you must also have a C compiler and zlib installed. -
\ No newline at end of file diff --git a/doc/building/llvm/GNULinux-GNAT.rst b/doc/building/llvm/GNULinux-GNAT.rst index b0f26b991..3733d763f 100644 --- a/doc/building/llvm/GNULinux-GNAT.rst +++ b/doc/building/llvm/GNULinux-GNAT.rst @@ -17,22 +17,10 @@ On Linux, GHDL is configured by ``configure`` and build by ``make``. .. rubric:: Example: .. code-block:: Bash - + cd <ghdl> mkdir build cd build ../configure --prefix=PREFIX make sudo make install - - -.. TODO:: - You need to install LLVM (usually depends on :samp:`libedit`, see :ghdlsharp`29`). The supported versions are 3.5 till 3.9, but debugging is only supported with LLVM 3.5. - - - First configure GHDL with the proper arg :samp:`./configure --with-llvm-config`. If :samp:`llvm-config` is not in your path, you can specify it: :samp:`./configure --with-llvm-config=LLVM_INSTALL/bin/llvm-config`. - - .. HINT:: - If you want to have stack backtraces on errors (like assert failure or index of out bounds), you need to configure and build :samp:`libbacktrace` from GCC (you don't need to configure GCC). Then add the following arg to configure: :samp:`--with-backtrace-lib=/path-to-gcc-build/libbacktrace/.libs/libbacktrace.a` - - - Then build with :samp:`make` and install with :samp:`make install`. - diff --git a/doc/building/llvm/index.rst b/doc/building/llvm/index.rst index 4f60cd083..9f0bcc98a 100644 --- a/doc/building/llvm/index.rst +++ b/doc/building/llvm/index.rst @@ -11,11 +11,17 @@ LLVM Backend * 3.5 * 3.8 + * 3.9 + * 4.0 + * 5.0 * CLANG (Compiler front-end for LLVM) * 3.5 * 3.8 + * 3.9 + * 4.0 + * 5.0 .. rubric:: Supported platforms diff --git a/doc/building/mcode/index.rst b/doc/building/mcode/index.rst index 3dc80c2f9..7d850c4a3 100644 --- a/doc/building/mcode/index.rst +++ b/doc/building/mcode/index.rst @@ -1,6 +1,6 @@ .. _BUILD:mcode: -Mcode Backend +mcode Backend ############# The mcode backend is available for all supported platforms and is also the most diff --git a/doc/contribute.rst b/doc/contribute.rst index a362f57e0..eaccd1560 100644 --- a/doc/contribute.rst +++ b/doc/contribute.rst @@ -4,23 +4,32 @@ Contributing ############ -The first step might be to use GHDL and explore it's possibilities in an own project. If you are new to VHDL, see the :ref:`USING:QuickStart` for an introduction. Furthermore, we encourage you to read :ref:`USING:Invoking`, where the most commonly used options are explained. You can also check the complete :ref:`REF:Command`. +The first step might be to use GHDL and explore it's possibilities in an own project. If you are new to VHDL, see the +:ref:`USING:QuickStart` for an introduction. Furthermore, we encourage you to read :ref:`USING:Invoking`, where the most +commonly used options are explained. You can also check the complete :ref:`REF:Command`. -If you are more familiar with GHDL, you might start asking yourself how it works internally. Then, you might find :ref:`Implementation of VHDL <REF:ImplVHDL>` and :ref:`Implementation of VITAL <REF:ImplVITAL>` interesting. +If you are more familiar with GHDL, you might start asking yourself how it works internally. Then, you might find +:ref:`Implementation of VHDL <REF:ImplVHDL>` and :ref:`Implementation of VITAL <REF:ImplVITAL>` interesting. -While using GHDL, you might find flaws, such as bugs, missing features, typos in the documentation or topics which are still not covered. In order to improve GHDL, we welcome bug reports, suggestions and contributions for any aspect of GHDL. Either if it's a bug or an enhancement, have a look at the |SHIELD:issues-open| and |SHIELD:issues-closed| to see if someone already told us about it. You might find a solution there. To get a broader view, you can also check the :ref:`Roadmap <CHANGE>`. +While using GHDL, you might find flaws, such as bugs, missing features, typos in the documentation or topics which are +still not covered. In order to improve GHDL, we welcome bug reports, suggestions and contributions for any aspect of +GHDL. Either if it's a bug or an enhancement, have a look at the |SHIELD:issues-open| and |SHIELD:issues-closed| to see +if someone already told us about it. You might find a solution there. To get a broader view, you can also check the +:ref:`Roadmap <CHANGE>`. -If you found no information on your topic, please, report so that we are aware! You can reach us through various ways: |SHIELD:gitter|, open a |SHIELD:issues-new| and/or subscribe to |SHIELD:mailing| +If you found no information on your topic, please, report so that we are aware! You can reach us through various ways: +|SHIELD:gitter|, open a |SHIELD:issues-new| and/or subscribe to |SHIELD:mailing| -.. HINT:: Since the development of GHDL started fifteen years ago, multiple platforms have been used as a support for both distribution and getting feedback. However, the development is now centralized in |SHIELD:gh-logo|. +.. HINT:: + Since the development of GHDL started fifteen years ago, multiple platforms have been used as a support for both distribution and getting feedback. However, the development is now centralized in |SHIELD:gh-logo|. - Therefore it is suggested to use the channels listed above instead of `gna.org/bugs/?=group=ghdl <https://gna.org/bugs/?group=ghdl>`_ or `sourceforge.net/p/ghdl-updates/tickets <https://sourceforge.net/p/ghdl-updates/tickets/>`_ . Still, these are checked from time to time. + Therefore it is suggested to use the channels listed above instead of `gna.org/bugs/?=group=ghdl <https://gna.org/bugs/?group=ghdl>`_ or `sourceforge.net/p/ghdl-updates/tickets <https://sourceforge.net/p/ghdl-updates/tickets/>`_ . Still, these are checked from time to time. .. TIP:: - `How To Ask Questions The Smart Way <www.catb.org/~esr/faqs/smart-questions.html>`_ - + `How To Ask Questions The Smart Way <www.catb.org/~esr/faqs/smart-questions.html>`_ + .. _reporting_bugs: - + Reporting bugs ============== @@ -30,31 +39,32 @@ Reporting bugs * If the executable created from your VHDL sources crashes, this may be a bug at runtime or the code itself may be wrong. However, since VHDL has a notion of pointers, an erroneous VHDL program (using invalid pointers for example) may crash. * If a compiler message is not clear enough, please tell us. The error messages can be improved, but we have not enough experience with them. -Please, report issues of this kind through |SHIELD:issues-new|, as this allows us to categorize issues into groups and assign developers to them. You can track the issue’s state and see how it’s getting solved. +Please, report issues of this kind through |SHIELD:issues-new|, as this allows us to categorize issues into groups and +assign developers to them. You can track the issue’s state and see how it’s getting solved. .. IMPORTANT:: - To make it easier, please elaborate a `Minimum (non) Working Example` (`MWE <https://en.wikipedia.org/wiki/Minimal_Working_Example>`_) prior to sending the report, so that the possible bug source is isolated. Shall the MWE compile and run, it is a good idea to make it look like a test and make an assert statement should finish the execution; the severity level `note` indicates success, while a severity level `failure` indicates failure. - + To make it easier, please elaborate a `Minimum (non) Working Example` (`MWE <https://en.wikipedia.org/wiki/Minimal_Working_Example>`_) prior to sending the report, so that the possible bug source is isolated. Shall the MWE compile and run, it is a good idea to make it look like a test and make an assert statement should finish the execution; the severity level `note` indicates success, while a severity level `failure` indicates failure. + Then, please include enough information for the maintainers to reproduce the problem. This includes: - + * Operating system and version of GHDL (you can get it with :samp:`ghdl --version`). - * Whether you have built GHDL from sources (provide short SHA of the used commit) or used the binary distribution (teel which realease/tag). - + * Whether you have built GHDL from sources (provide short SHA of the used commit) or used the binary distribution (tell which release/tag). + * If you cannot compile, please report which compiler you are using and the version. - + * Content of the input files which make the MWE * Description of the problem: - + * Comment explaining whether the MWE should compile or not; if yes, whether or not is should run until the assertion. * What you expected to happen and what you actually get. If you know the LRM well enough, please specify the paragraph which might be not well implemented. * Samples of any log. * Anything else that you think would be helpful. -.. NOTE:: If you don't know the LRM, be aware that an issue claimed as bug report may be rejected because there is no bug according to it. GHDL aims at implementing VHDL as defined in `IEEE 1076 <http://ieeexplore.ieee.org/document/4772740/>`_. However, some other tools allow constructs which do not fully follow the standard revisions. Therefore, comparisons with other VHDL is not a solid argument. Some of them are supported by GHDL (see :ref:`IEEE_library_pitfalls`), but any such enhancement will have very low priority. - +.. NOTE:: + If you don't know the LRM, be aware that an issue claimed as bug report may be rejected because there is no bug according to it. GHDL aims at implementing VHDL as defined in `IEEE 1076 <http://ieeexplore.ieee.org/document/4772740/>`_. However, some other tools allow constructs which do not fully follow the standard revisions. Therefore, comparisons with other VHDL is not a solid argument. Some of them are supported by GHDL (see :ref:`IEEE_library_pitfalls`), but any such enhancement will have very low priority. .. _requesting_enhancements: - + Requesting enhancements ======================= @@ -65,10 +75,12 @@ All enhancements and feature requests are welcome. Please `open a new issue <htt Improving the documentation =========================== -If you found a mistake in the documentation, please send a comment. If you didn't understand some parts of this manual, please tell us. English is not our mother tongue, so this documentation may not be well-written. - -Likewise, rewriting part of the documentation or missing content (such as, examples) is a good way to improve it. Since it automatically is built from `reStructuredText` and `Markdown` sources, you can fork, modify and request the maintainers to pull your copy. See :ref:`pull_request`. +If you found a mistake in the documentation, please send a comment. If you didn't understand some parts of this manual, +please tell us. English is not our mother tongue, so this documentation may not be well-written. +Likewise, rewriting part of the documentation or missing content (such as, examples) is a good way to improve it. Since +it automatically is built from `reStructuredText` and `Markdown` sources, you can fork, modify and request the +maintainers to pull your copy. See :ref:`pull_request`. .. _pull_request: @@ -77,9 +89,11 @@ Fork, modify and pull-request .. TIP:: * Before starting any modification, you might want to have a look at |SHIELD:issues-pr| and |SHIELD:issues-pr-closed|, to check which other contributions are being made or have been made. If you observe that the modifications you are about to start might conflict with any other, please |SHIELD:gitter| or open a |SHIELD:issues-new| to coordinate. - * See section :ref:`'BUILD:dir_structure'` to faster find the location of the sources you need to modify, and/or to know where to place new ones. + * See section :ref:`BUILD:dir_structure` to faster find the location of the sources you need to modify, and/or to know where to place new ones. -Contributing source code/documentation via `Git <https://git-scm.com/>`_ is very easy. Although we don't provide direct write access to our repositories, the project is hosted at GitHub, which follows a fork, edit and pull-request `flow <https://help.github.com/articles/github-flow/>`_ . That is: +Contributing source code/documentation via `Git <https://git-scm.com/>`_ is very easy. Although we don't provide direct +write access to our repositories, the project is hosted at GitHub, which follows a fork, edit and pull-request +`flow <https://help.github.com/articles/github-flow/>`_ . That is: 1. Make a copy (`fork <https://help.github.com/articles/fork-a-repo/>`_) of the project. 2. Do the changes you wish (edit, add, rename, move and/or delete). @@ -94,4 +108,4 @@ Contributing source code/documentation via `Git <https://git-scm.com/>`_ is very Related interesting projects ============================ -If you have an interesting project, please send us feedback or get listed on our :ref:`INTRO:WHO` page. +If you have an interesting project, please send us feedback or get listed on our :ref:`INTRO:WHO` page. diff --git a/doc/getting/Docker.rst b/doc/getting/Docker.rst deleted file mode 100644 index 6ba61dbd8..000000000 --- a/doc/getting/Docker.rst +++ /dev/null @@ -1,35 +0,0 @@ -.. _DOCKER: - -Docker containers -################# - -* :ghdlsharp:`270` -* :ghdlsharp:`272` -* :ghdlsharp:`297` - -What is docker? A primer -======================== - -Where are images hosted? -======================== - -docker-hub -ghdl-tools -Dockerfiles - -Launch options -============== - -With(out) shared folder ------------------------ - -Interactive/daemon ------------------- - -Shrinking ---------- - -Additional tools, with(out) GUI -------------------------------- - -GtkWave, PoC, VUnit, OSVVM, UVVM
\ No newline at end of file diff --git a/doc/getting/Releases.rst b/doc/getting/Releases.rst index 63284307a..7d3a91929 100644 --- a/doc/getting/Releases.rst +++ b/doc/getting/Releases.rst @@ -1,14 +1,14 @@ .. _RELEASE: -Releases -######## +Releases and sources +#################### .. contents:: Contents of this Page :local: .. _RELEASE:packages: -Downloading pre-build packages +Downloading pre-built packages ****************************** .. |Ubu1204-llvm38| image:: https://img.shields.io/github/downloads/tgingold/ghdl/2017-03-01/ghdl-0.34-dev-llvm-3.8-2017-03-01-ubu1204.tgz.svg @@ -41,8 +41,6 @@ Downloading pre-build packages | Windows x86 | mcode | 5.25 MiB | |Win32-mcode| | +--------------+----------+-----------+--------------------+ - - .. _RELEASE:Sources: Downloading Source Files @@ -156,17 +154,3 @@ protocol: git clone "ssh://git@github.com:tgingold/ghdl.git" ghdl cd ghdl git remote rename origin github - - ---------------------------------------------------------------------- - -.. TODO:: - - * Naming: - * branch ghdl-X.Y - * tag vX.Y - * stable, development, nightly - * Regular: ubuntu-mcode and fedora-llvm (both latest default packages). - * Distro checking: three distros and three compilers, nine options total. Would you add Debian? Any other? - * Dependency version checking: single distro and specific compiler and version pairs. Which ones? LLVM 3.5? LLVM3.9? LLVM 4? GGC 4? GCC 5? - * Release: does it make any sense to realease multiple distro versions, if all of them are compiled with the same dependency version? A side observation is that Fedora's release is half the size of Ubuntu's, even though both are compiled with LLVM 3.8. Why?
\ No newline at end of file diff --git a/doc/index.rst b/doc/index.rst index 17b95dc2e..f7c84f95d 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -17,14 +17,17 @@ LRM) is a plus. News **** + 15.08.2017 - GHDL 0.34 was released. + ==================================== + 23.10.2015 - GHDL 0.33 was released. ==================================== .. only:: latex - .. rubric:: 23.10.2015 - GHDL 0.33 was released. + .. rubric:: 15.08.2017 - GHDL 0.34 was released. -Lorem ipsum dolor sit amet... + .. rubric:: 23.10.2015 - GHDL 0.33 was released. .. |docdate| date:: %b %d, %Y - %H:%M @@ -36,11 +39,9 @@ Lorem ipsum dolor sit amet... :caption: Introduction :hidden: - intro/WhatIsVHDL - intro/WhatIsGHDL - intro/Contributing - intro/Copyrights - License/gpl-2.0 + about + contribute + licenses .. raw:: latex @@ -63,7 +64,7 @@ Lorem ipsum dolor sit amet... :hidden: getting/Releases - Building GHDL building/building> + Building GHDL <building/Building> building/PrecompileVendorPrimitives .. raw:: latex @@ -88,6 +89,5 @@ Lorem ipsum dolor sit amet... :hidden: appendix/Roadmap - appendix/Changelog appendix/Meta genindex diff --git a/doc/references/CommandReference.rst b/doc/references/CommandReference.rst index 3816afe42..16430cb72 100644 --- a/doc/references/CommandReference.rst +++ b/doc/references/CommandReference.rst @@ -11,8 +11,6 @@ Environment variables .. envvar:: GHDL_PREFIX - .. TODO:: Add short description to :option:`GHDL_PREFIX` - Misc commands ============= @@ -34,7 +32,7 @@ for this later command are displayed:: ghdl -h command .. index:: cmd display configuration - + Display config [``--disp-config``] -------------------------------------- @@ -136,7 +134,7 @@ Link [``--link``] --------------------- .. option:: --link <[options] primary_unit [secondary_unit]> - + Performs only the second stage of the elaboration command: the executable is created by linking the files of the object files list. This command is available only for completeness. The elaboration command is equivalent to the bind command followed by the link command. .. index:: cmd GCC/LLVM list link @@ -176,7 +174,7 @@ Use ``COMMAND`` as the command name for the assembler. If ``COMMAND`` is not a .. option:: --LINK<=COMMAND> Use ``COMMAND`` as the linker driver. If ``COMMAND`` is not a path, then it is searched in the path. The default is ``gcc``. - + Passing options to other programs ================================= diff --git a/doc/using/InvokingGHDL.rst b/doc/using/InvokingGHDL.rst index 0bfa2d969..dd50a5874 100644 --- a/doc/using/InvokingGHDL.rst +++ b/doc/using/InvokingGHDL.rst @@ -56,16 +56,16 @@ Re-analyzes all the configurations, entities, architectures and package declarat * a configuration unit * an entity unit * an entity unit followed by a name of an architecture unit - + Name of the units must be a simple name, without any dot. You can select the name of the `WORK` library with the :option:`--work=NAME` option, as described in :ref:`GHDL_options`. See section ':ref:`Top_entity`', for the restrictions on the root design of a hierarchy. - + * If the GCC/LLVM backend was enabled during the compilation of GHDL, the elaboration command creates an executable containing the code of the VHDL sources, the elaboration code and simulation code to execute a design hierarchy. The executable is created in the current directory and the the filename is the name of the primary unit, or for the later case, the concatenation of the name of the primary unit, a dash, and the name of the secondary unit (or architecture). Option :option:`-o` followed by a filename can override the default executable filename. * If mcode is used, this command elaborates the design but does not generate anything. Since the run command also elaborates the design, this con be skipped. .. index:: cmd run - + Run [``-r``] ---------------- @@ -188,6 +188,17 @@ Generate Makefile [``--gen-makefile``] This command works like the make command (see :option:`-m`), but only a makefile is generated on the standard output. +.. index:: --gen-depends command + +Generate dependency file command [``--gen-depends``] +------------------------- + +.. option:: --gen-depends <[options] primary [secondary]> + +Generate a Makefile containing only dependencies to build a design unit. + +This command works like the make and gen-makefile commands (see :option:`-m`), but instead of a full makefile only dependencies without rules are generated on the standard output. +Theses rules can then be integrated in another Makefile. Options ======= diff --git a/doc/using/QuickStartGuide.rst b/doc/using/QuickStartGuide.rst index b390b382e..a1afa00b2 100644 --- a/doc/using/QuickStartGuide.rst +++ b/doc/using/QuickStartGuide.rst @@ -216,13 +216,3 @@ Unless you are only studying VHDL, you will work with larger designs than the on * Remove the :file:`work/` directory: ``rm -rf work``. Only the executable is kept. If you want to rebuild the design, create the :file:`work/` directory, import the sources, and make the design. .. WARNING:: Sometimes, a design does not fully follow the VHDL standards. For example it uses the badly engineered ``std_logic_unsigned`` package. GHDL supports this VHDL dialect through some options: ``--ieee=synopsys -fexplicit``. See section ':ref:`IEEE_library_pitfalls`', for more details. - -Further examples -======================= - -.. TODO:: - - * Add references to examples/tutorials with GHDL. - * Shall `René Doß <https://mail.gna.org/public/ghdl-discuss/2017-01/msg00000.html>` want to contribute adapting his article to RST? - * https://github.com/Obijuan/open-fpga-verilog-tutorial/wiki ->>>>>>> doc/changelog renamed to doc/appendix diff --git a/doc/using/Simulation.rst b/doc/using/Simulation.rst index 968849ee7..c6f49bec7 100644 --- a/doc/using/Simulation.rst +++ b/doc/using/Simulation.rst @@ -102,16 +102,24 @@ all options available, including the debugging one. See section ':ref:`Backannotation`', for more details. +.. option:: --vpi<=FILENAME> + +Load VPI module. + +.. option:: --vpi-trace<=FILE> + +Trace vpi calls to FILE. + .. option:: --help Display a short description of the options accepted by the runtime library. .. _export_waves: - + Export waveforms ================ -.. option:: --read-opt-file<=FILENAME> +.. option:: --read-wave-opt=<FILENAME> Filter signals to be dumped to the wave file according to the wave option file provided. @@ -144,7 +152,7 @@ Export waveforms # those of sub3) /**/sub3/*/* -.. option:: --write-opt-file<=FILENAME> +.. option:: --write-wave-opt=<FILENAME> If the wave option file doesn't exist, creates it with all the signals of the design. Otherwise throws an error, because it won't erase an existing @@ -206,7 +214,7 @@ Export waveforms .. option:: --vcd-nodate Do not write date in VCD file - + .. option:: --fst<=FILENAME> Write the waveforms into a `fst`, that can be displayed by @@ -223,16 +231,10 @@ Export waveforms It may change slightly. The ``gtkwave`` tool can read the GHW files. Contrary to VCD files, any VHDL type can be dumped into a GHW file. - -.. TODO:: - - Brief explanation on why these three formats where chosen only. Explain why other formats add no functionality. - - Interactive simulation (GtkWave) is only possible with VCD. - - `Source code annotation is currently not available for VHDL, however all of GTKWave's other debug features are readily accessible. VHDL support is planned for a future release`. That's something that could be added in the future, but I have no plan for it. - Export hierarchy and references =============================== - + .. option:: --disp-tree<[=KIND]> .. index:: display design hierarchy @@ -257,7 +259,7 @@ Export hierarchy and references .. option:: --no-run - Stop the simulation before the first cycle. This may be used with :option:`--disp-tree` to display the tree without simulating the whole design. This option actually elaborates the design, so it will catch any bound error in port maps. + Stop the simulation before the first cycle. This may be used with :option:`--disp-tree` to display the tree without simulating the whole design. This option actually elaborates the design, so it will catch any bound error in port maps. .. option:: --xref-html <[options] file...> @@ -268,16 +270,13 @@ The set of ``file`` are analyzed, and then, if the analysis is successful, html * If the option :option:`--format=html2` is specified, then the generated html files follow the HTML 2.0 standard, and colours are specified with `<FONT>` tags. However, colours are hard-coded. * If the option :option:`--format=css` is specified, then the generated html files follow the HTML 4.0 standard, and use the CSS-1 file :file:`ghdl.css` to specify colours. This file is generated only if it does not already exist (it is never overwritten) and can be customized by the user to change colours or appearance. Refer to a generated file and its comments for more information. - + .. option:: --psl-report<=FILENAME> Write a report for PSL at the end of simulation. For each PSL cover and assert statements, the name, source location and whether it passed or failed is reported. The file is written using the JSON format, but still being human readable. - -.. TODO:: - * Maybe worth adding a small example of how to generate a JSON file? - + .. option:: --file-to-xml - + Outputs an XML representation of the decorated syntax tree for the input file and its dependencies. It can be used for VHDL tooling using semantic information, like style checkers, documentation extraction, complexity estimation... .. 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rd : out std_logic; - --out - wdata : out std_logic_vector(7 downto 0); - wr_en : in std_logic; - wr : out std_logic - ); -end; - -architecture Behavioral of capitalisation is - - - -begin - - - process(clk) - begin - wr<='0'; - rd<='0'; - if wr_en='1' and rd_en ='1' then - wr<='1'; - rd<='1'; - if (unsigned(rdata)>X"60") and - (unsigned(rdata)<X"7B") then - wdata<=rdata(7 downto 6 )&'0'& rdata(4 downto 0); - else - wdata<=rdata; - end if; - end if; - if reset='1' then - wr<='0'; - end if; - end process; - - - -end Behavioral; - diff --git a/doc/using/UART_srcs/capitalisation/makefile b/doc/using/UART_srcs/capitalisation/makefile deleted file mode 100644 index ad8a01b04..000000000 --- a/doc/using/UART_srcs/capitalisation/makefile +++ /dev/null @@ -1,18 +0,0 @@ -all: - rm -rf work - mkdir work - - ghdl -a --work=work --workdir=work top_capitalisation.vhd - ghdl -a --work=work --workdir=work capitalisation.vhd - ghdl -a --work=work --workdir=work ../rx/UART_RX_8N1.vhd - ghdl -a --work=work --workdir=work ../tx/UART_TX_8N1.vhd - ghdl -a --work=work --workdir=work capitalisation.vhd - - ghdl -a --work=work --workdir=work tb_capitalisation.vhd - ghdl -e --workdir=work -Pwork tb_capitalisation - ghdl -r tb_capitalisation --wave=tbench.ghw --stop-time=700us - - -view: - gtkwave tbench.ghw a.gtkw - diff --git a/doc/using/UART_srcs/capitalisation/tb_capitalisation.vhd b/doc/using/UART_srcs/capitalisation/tb_capitalisation.vhd deleted file mode 100644 index 364142946..000000000 --- a/doc/using/UART_srcs/capitalisation/tb_capitalisation.vhd +++ /dev/null @@ -1,89 +0,0 @@ --- tb_capitalisation.vhd ----------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity tb_capitalisation is -end tb_capitalisation; - -architecture behavior of tb_capitalisation is - - constant board_clk_period : time := 10 ns; - constant board_clk_freq: integer :=100E6; --100MHz - - signal board_clk : std_logic := '0'; - signal reset : std_logic := '0'; - signal rx : std_logic := '1'; - signal tx : std_logic; - - procedure tx_char (signal txpin : out std_logic; - txdata : in character; baudrate : in integer) is - constant bittime : time := (integer(1000000000.0/real(baudrate))) * 1 ns; - variable c : std_logic_vector(7 downto 0); - begin - c := std_logic_vector(to_unsigned(character'pos(txdata), 8)); - txpin <= '0'; -- Startbit - wait for bittime; - for i in 0 to 7 loop - txpin <= c(i); - wait for bittime; - end loop; - txpin <= '1'; -- Stopbit - wait for bittime; - end tx_char; - - -- Component Declaration for the Unit Under Test (UUT) -component top_capitalisation is - generic (clk_freq : integer; - baudrate : integer); - port( - board_clk : in std_logic ; - reset : in std_logic ; - rx : in std_logic ; - tx : out std_logic ); -end component; - -begin - -- Instantiate the Unit Under Test (UUT) -UART_example: top_capitalisation - generic map ( - clk_freq => board_clk_freq, - baudrate =>115200) - port map( - board_clk => board_clk, - reset => reset, - rx => rx, - tx => tx ); - - process - begin - wait for 80000 ns; - tx_char(RX, '$', 115200); - tx_char(RX, 'g', 115200); - tx_char(RX, '#', 115200); - wait for 50 us; - tx_char(RX, 'b', 115200); - tx_char(RX, 'c', 115200); - wait; -- will wait forever - end process; - - -- Clock process definitions - board_clk_process : process - begin - board_clk <= '0'; - wait for board_clk_period/2; - board_clk <= '1'; - wait for board_clk_period/2; - end process; - - -- Stimulus process - process - begin - reset <= '1'; - wait for 100 ns; - reset <='0'; - wait; - end process; - -end; diff --git a/doc/using/UART_srcs/capitalisation/top_capitalisation.vhd b/doc/using/UART_srcs/capitalisation/top_capitalisation.vhd deleted file mode 100644 index 01c8e3585..000000000 --- a/doc/using/UART_srcs/capitalisation/top_capitalisation.vhd +++ /dev/null @@ -1,126 +0,0 @@ --- top_capitalisation.vhd ----------------------------------------------------------------------- - --- top_capitalisation --- | --- + capitalisation --- + UART_8N1_RX --- + UART_8N1_TX - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity top_capitalisation is - generic (clk_freq : integer; - baudrate : integer); - port( - board_clk : in std_logic ; - reset : in std_logic ; - rx : in std_logic ; - tx : out std_logic ); -end top_capitalisation; - -architecture behavior of top_capitalisation is - signal rd_en : std_logic; - signal rdata : std_logic_vector (7 downto 0); - signal rd : std_logic; - - signal wr_en : std_logic; - signal wdata : std_logic_vector (7 downto 0); - signal wr : std_logic; - -component capitalisation is - port( - clk : in std_logic; - reset : in std_logic; - --in - rdata : in std_logic_vector(7 downto 0); - rd_en : in std_logic; - rd : out std_logic; - --out - wdata : out std_logic_vector(7 downto 0); - wr_en : in std_logic; - wr : out std_logic - ); -end component; - -component UART_8N1_RX is - generic (clk_freq : integer; - baudrate : integer); - port( - clk : in std_logic; - reset : in std_logic; - --8bit interface - rdata : out std_logic_vector(7 downto 0); - rd : in std_logic; - rd_en : out std_logic; - --physical wire RX - rx : in std_logic - ); -end component; - -component UART_8N1_TX is - generic( - clk_freq : integer; - baudrate : integer; - addr_depth : integer:=5); - port( - clk : in std_logic; - reset : in std_logic; - --8bit interface - wdata : in std_logic_vector(7 downto 0); - wr : in std_logic; - wr_en : out std_logic; - - --physical wire - tx : out std_logic); -end component; - - -begin - -UART_RX:UART_8N1_RX - generic map ( - clk_freq => clk_freq, - baudrate =>115200) - port map( - clk => board_clk, - reset => reset, - rdata => rdata, - rd => rd, - rd_en => rd_en, - --physical wire RX - rx => rx - ); - -trans: capitalisation - port map( - clk => board_clk, - reset => reset, - --in - rdata => rdata, - rd_en => rd_en, - rd => rd, - --out - wdata => wdata, - wr_en => wr_en, - wr => wr - ); - -UART_TX: UART_8N1_TX - generic map( - clk_freq => clk_freq, - baudrate => 115200) - port map( - clk => board_clk, - reset => reset, - --8bit interface - wdata => wdata, - wr => wr, - wr_en => wr_en, - - --physical wire TX - tx => tx - ); -end; diff --git a/doc/using/UART_srcs/capitalisation/zeichnung.png b/doc/using/UART_srcs/capitalisation/zeichnung.png Binary files differdeleted file mode 100644 index f51a0fbdd..000000000 --- a/doc/using/UART_srcs/capitalisation/zeichnung.png +++ /dev/null diff --git a/doc/using/UART_srcs/file_in_out/Zeichnung.svg b/doc/using/UART_srcs/file_in_out/Zeichnung.svg deleted file mode 100644 index ae9e85d86..000000000 --- a/doc/using/UART_srcs/file_in_out/Zeichnung.svg +++ /dev/null @@ -1,290 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<!-- Created with Inkscape (http://www.inkscape.org/) --> - -<svg - xmlns:dc="http://purl.org/dc/elements/1.1/" - xmlns:cc="http://creativecommons.org/ns#" - xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" - xmlns:svg="http://www.w3.org/2000/svg" - xmlns="http://www.w3.org/2000/svg" - xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" - 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ghdl -r tb_file --wave=tbench.ghw --stop-time=200us - - -view: - gtkwave tbench.ghw a.gtkw - diff --git a/doc/using/UART_srcs/file_in_out/tb_file.vhd b/doc/using/UART_srcs/file_in_out/tb_file.vhd deleted file mode 100644 index fe18f6665..000000000 --- a/doc/using/UART_srcs/file_in_out/tb_file.vhd +++ /dev/null @@ -1,142 +0,0 @@ ---tb_file.vhd ------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY tb_file IS -END tb_file; ---vhdl no seek or rewind function in VHDL - -ARCHITECTURE behavior OF tb_file IS - -signal clk : std_logic := '0'; -signal reset : std_logic; - -signal rdata : std_logic_vector(7 downto 0); -signal rd_en : std_logic; -signal rd : std_logic; - -signal wdata : std_logic_vector(7 downto 0); -signal wr_en : std_logic:='1'; -signal wr : std_logic; - - -- Component Declaration for the Unit Under Test (UUT) -component capitalisation is - port( - clk : in std_logic; - reset : in std_logic; - --in - rdata : in std_logic_vector(7 downto 0); - rd_en : in std_logic; - rd : out std_logic; - --out - wdata : out std_logic_vector(7 downto 0); - wr_en : in std_logic; - wr : out std_logic - ); -end component; - - -- Clock period definitions - constant clk_period : time := 10 ns; - -subtype by_te is character; -type f_byte is file of by_te; - -BEGIN - -process(clk) -begin - if rising_edge (clk) then - if reset='0' then - wr_en<='1'; - else - wr_en<='0'; - end if; - end if; -end process; - ---read a file -process (reset,clk) -constant file_name: string:="test.txt"; -file in_file: f_byte open read_mode is file_name; - -variable a:character; - -begin - if reset='1' then - rd_en<='0'; - else - - if rising_edge(clk) then - if rd_en='0' or rd='1' then - if not endfile (in_file) then - read(in_file,a); - rdata<=std_logic_vector(to_unsigned(character'pos(a),8)); - --very tricky the conversation - rd_en<='1'; - else - rd_en<='0'; - end if; - end if; - end if; - --wait until rising_edge(CLK) and rd='1'; - end if; -end process; - - - ---write a file -process (clk) -constant file_name: string:="test1.txt"; -file out_file: f_byte open write_mode is file_name; - -----variable in_line,out_line: line; -variable b:character; - - begin - if rising_edge(CLK) then - if reset='0' then - if wr='1' then - b:=character'val(to_integer(unsigned(wdata))); - write(out_file,b); - end if; - end if; - end if; - end process; - - stim_proc : process - begin - reset <= '1'; - - wait for 50 ns; - reset <='0'; - - wait; - end process; - - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - -engine: capitalisation - port map( - - clk => clk, - reset => reset, - - rdata => rdata, - rd_en => rd_en, - rd => rd, - - wdata => wdata, - wr_en => wr_en, - wr => wr - ); - - -END; diff --git a/doc/using/UART_srcs/file_in_out/test.txt b/doc/using/UART_srcs/file_in_out/test.txt deleted file mode 100644 index 3ee58d9a3..000000000 --- a/doc/using/UART_srcs/file_in_out/test.txt +++ /dev/null @@ -1 +0,0 @@ -Hallo world! Can you see my text? diff --git a/doc/using/UART_srcs/file_in_out/test1.txt b/doc/using/UART_srcs/file_in_out/test1.txt deleted file mode 100644 index a868f3f93..000000000 --- a/doc/using/UART_srcs/file_in_out/test1.txt +++ /dev/null @@ -1 +0,0 @@ -HALLO WORLD! CAN YOU SEE MY TEXT? diff --git a/doc/using/UART_srcs/file_in_out/zeichnung.png b/doc/using/UART_srcs/file_in_out/zeichnung.png Binary files differdeleted file mode 100644 index e849417f4..000000000 --- a/doc/using/UART_srcs/file_in_out/zeichnung.png +++ /dev/null diff --git a/doc/using/UART_srcs/rx/UART_RX_8N1.vhd b/doc/using/UART_srcs/rx/UART_RX_8N1.vhd deleted file mode 100644 index a7fe757a5..000000000 --- a/doc/using/UART_srcs/rx/UART_RX_8N1.vhd +++ /dev/null @@ -1,150 +0,0 @@ --- UART_RX_8N1.vhd ----------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use ieee.numeric_std.all; - - -entity UART_8N1_RX is - - generic (clk_freq : integer; - baudrate : integer); - port( - clk : in std_logic; - reset : in std_logic; - --8bit interface - rdata : out std_logic_vector(7 downto 0); - rd : in std_logic; - rd_en : out std_logic; - --physical wire RX - rx : in std_logic - ); -end UART_8N1_RX; - - -architecture Behavioral of UART_8N1_RX is - - type state_type is (idle, start, data0, data1, data2, data3, data4, - data5, data6, data7, stop); - signal state : state_type; - - signal puffer : std_logic_vector (7 downto 0); - ---FIFO - type RAM is array (0 to 63) of std_logic_vector (7 downto 0); - - signal fifo : RAM ; - - signal nextwrite : unsigned(5 downto 0); - signal nextread : unsigned(5 downto 0); - - constant tick : integer := clk_freq/baudrate; - signal tick_counter : integer range 0 to (tick+1); - - -begin - - rdata <= fifo(to_integer(nextread)); - - process (clk) - begin - if rising_edge(clk) then - if rd = '1' then - nextread <= nextread+1; - end if; - if reset = '1' then - nextread <= (others => '0'); - end if; - end if; - end process; - - rd_en<= '0' when nextread=nextwrite else '1'; - - - process(clk) - begin - - if (clk'event and clk = '1') then - tick_counter <= tick_counter + 1; - - case state is - - when idle => - tick_counter <= 0; - if (rx = '0') then --check start condtion - state <= start; - else - state <= idle; - end if; - - when start => - if (tick_counter = tick/2) then --capture in the middle - tick_counter <= 0; - state <= data0; - end if; - - when data0 => - if (tick_counter = tick) then - puffer (0) <= rx; - tick_counter <= 0; - state <= data1; - end if; - when data1 => - if (tick_counter = tick) then - puffer (1) <= rx; - tick_counter <= 0; - state <= data2; - end if; - when data2 => - if (tick_counter = tick) then - puffer (2) <= rx; - tick_counter <= 0; - state <= data3; - end if; - when data3 => - if (tick_counter = tick) then - puffer(3) <= rx; - tick_counter <= 0; - state <= data4; - end if; - when data4 => - if (tick_counter = tick) then - puffer (4) <= rx; - tick_counter <= 0; - state <= data5; - end if; - when data5 => - if (tick_counter = tick) then - puffer (5) <= rx; - tick_counter <= 0; - state <= data6; - end if; - when data6 => - if (tick_counter = tick) then - puffer (6) <= rx; - tick_counter <= 0; - state <= data7; - end if; - when data7 => - if (tick_counter = tick) then - puffer (7) <= rx; - tick_counter <= 0; - state <= stop; - end if; - when stop => - if (tick_counter = tick) then - fifo(to_integer(nextwrite)) <= puffer; - nextwrite <= nextwrite+1; - tick_counter <= 0; - state <= idle; - end if; - end case; - if reset='1' then - state <=idle; - nextwrite <= (others => '0'); - end if; - end if; - - end process; -end Behavioral; - diff --git a/doc/using/UART_srcs/rx/makefile b/doc/using/UART_srcs/rx/makefile deleted file mode 100644 index 3546a42ad..000000000 --- a/doc/using/UART_srcs/rx/makefile +++ /dev/null @@ -1,8 +0,0 @@ - -all: - ghdl -i *.vhd - ghdl -m tb_UART_RX_8N1 - ghdl -r tb_UART_RX_8N1 --stop-time=800us --wave=RX.ghw - -view: - gtkwave RX.ghw diff --git a/doc/using/UART_srcs/rx/sim_RX.png b/doc/using/UART_srcs/rx/sim_RX.png Binary files differdeleted file mode 100644 index 5062d26a3..000000000 --- a/doc/using/UART_srcs/rx/sim_RX.png +++ /dev/null diff --git a/doc/using/UART_srcs/rx/tb_UART_RX_8N1.vhd b/doc/using/UART_srcs/rx/tb_UART_RX_8N1.vhd deleted file mode 100644 index 4fd67c8e7..000000000 --- a/doc/using/UART_srcs/rx/tb_UART_RX_8N1.vhd +++ /dev/null @@ -1,121 +0,0 @@ --- tb_UART_RX_8N1.vhd ----------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -entity tb_UART_RX_8N1 is -end tb_UART_RX_8N1; - -architecture behavior of tb_UART_RX_8N1 is - - signal board_clk : std_logic := '0'; - signal reset : std_logic := '0'; - signal rx : std_logic := '1'; - signal rd : std_logic := '0'; - signal rd_en : std_logic; - signal data : std_logic_vector (7 downto 0); - - procedure tx_char (signal txpin : out std_logic; - txdata : in character; baudrate : in integer) is - constant bittime : time := (integer(1000000000.0/real(baudrate))) * 1 ns; - variable c : std_logic_vector(7 downto 0); - begin - c := std_logic_vector(to_unsigned(character'pos(txdata), 8)); - txpin <= '0'; -- Startbit - wait for bittime; - for i in 0 to 7 loop - txpin <= c(i); - wait for bittime; - end loop; - txpin <= '1'; -- Stopbit - wait for bittime; - end tx_char; - --Outputs - -component UART_8N1_RX is - - generic (clk_freq : integer; - baudrate : integer); - port( - clk : in std_logic; - reset : in std_logic; - --8bit interface - rdata : out std_logic_vector(7 downto 0); - rd : in std_logic; - rd_en : out std_logic; - --physical wire RX - rx : in std_logic - ); -end component; - - constant board_clk_period : time := 10 ns; - constant board_clk_freq: integer :=100E6; --100MHz - -begin - - -- Instantiate the Unit Under Test (UUT) -UART_RX:UART_8N1_RX - - generic map ( - clk_freq => board_clk_freq, - baudrate =>115200) - port map( - clk => board_clk, - reset => reset, - rdata => data, - rd => rd, - rd_en => rd_en, - --physical wire RX - rx => rx - ); - - process - begin - wait for 80000 ns; - tx_char(RX, '$', 115200); - tx_char(RX, 'g', 115200); - tx_char(RX, '#', 115200); - wait for 50 us; - tx_char(RX, '6', 115200); - tx_char(RX, '7', 115200); - wait; -- will wait forever - end process; - - -- Clock process definitions - board_clk_process : process - begin - board_clk <= '0'; - wait for board_clk_period/2; - board_clk <= '1'; - wait for board_clk_period/2; - end process; - - -- Stimulus process - process - begin - reset <= '1'; - wait for 100 ns; - reset <='0'; - wait; - end process; - - -- Stimulus process - stim_proc : process - begin - - loop - wait for 200 us; - wait until rising_edge(board_clk); - if rd_en='1' then - rd<= '1'; - end if; - wait until rising_edge(board_clk); - rd<= '0'; - end loop; - - wait; - end process; - - end; diff --git a/doc/using/UART_srcs/tx/BlockTX.png b/doc/using/UART_srcs/tx/BlockTX.png Binary files differdeleted file mode 100644 index 9031bb2f3..000000000 --- a/doc/using/UART_srcs/tx/BlockTX.png +++ /dev/null diff --git a/doc/using/UART_srcs/tx/TX.ghw b/doc/using/UART_srcs/tx/TX.ghw Binary files differdeleted file mode 100644 index 1af3cfed0..000000000 --- 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std_logic_vector(7 downto 0); - wr : in std_logic; - wr_en : out std_logic; - - --physical wire - tx : out std_logic); -end; - - -architecture Behavioral of UART_8N1_TX is ---FSM - type state_type is (idle, start, data0, data1, data2, data3, data4, - data5, data6, data7, stop); - - signal state : state_type := idle; - signal nextstate : state_type := idle; - - --FIFO - type RAM is array (0 to (2**(addr_depth)-1)) of std_logic_vector (7 downto 0); - signal fifo : RAM; - signal nextwrite : unsigned((addr_depth-1) downto 0); - signal nextread : unsigned((addr_depth-1) downto 0); - - signal send_empty: std_logic; - - --output - signal data_tx : std_logic_vector (7 downto 0); - constant tick : integer := (clk_freq/baudrate); - signal tick_counter : integer range 0 to (tick+1); - -begin - - wr_en <= '0' when (nextwrite+1 = nextread) else '1'; - send_empty<='1' when nextwrite=nextread else '0'; - - process(clk) - begin - if rising_edge(clk) then - if reset = '1' then - nextread <= (others => '0'); - elsif state = stop and nextstate = idle then - nextread <= nextread+1; - end if; - end if; - end process; - - process(clk) - begin - if rising_edge(clk) then - state <= nextstate; - end if; - end process; - - process(clk) - begin - if rising_edge(clk) then - if reset = '1' then - nextwrite <= (others => '0'); - elsif wr = '1' then - fifo(to_integer(nextwrite)) <= wdata; - nextwrite <= nextwrite+1; - - end if; - end if; - end process; - - - data_tx <= fifo(to_integer(nextread)); - - process(clk) - begin - if rising_edge(clk) then - if state = idle then - if nextwrite /= nextread then - nextstate <= start; - tick_counter <= 0; - tx <= '0'; - else - tx <= '1'; - end if; - else - if tick_counter = tick then - tick_counter <= 0; - else - tick_counter <= tick_counter + 1; - end if; - end if; - if tick_counter = tick then - if state = start then - nextstate <= data0; - tx <= data_tx(0); - end if; - - if state = data0 then - nextstate <= data1; - tx <= data_tx(1); - end if; - - if state = data1 then - nextstate <= data2; - tx <= data_tx(2); - end if; - - if state = data2 then - nextstate <= data3; - tx <= data_tx(3); - end if; - if state = data3 then - nextstate <= data4; - tx <= data_tx(4); - end if; - if state = data4 then - nextstate <= data5; - tx <= data_tx(5); - end if; - if state = data5 then - nextstate <= data6; - tx <= data_tx(6); - end if; - if state = data6 then - nextstate <= data7; - tx <= data_tx(7); - end if; - if state = data7 then - nextstate <= stop; - tx <= '1'; - end if; - if state = stop then - nextstate <= idle; - tx <= '1'; - end if; - end if; - - if reset = '1' then - tick_counter <= 0; - tx <= '1'; - nextstate <= idle; - end if; - end if; - - end process; - - -end Behavioral; - diff --git a/doc/using/UART_srcs/tx/makefile b/doc/using/UART_srcs/tx/makefile deleted file mode 100644 index 83168f2f1..000000000 --- a/doc/using/UART_srcs/tx/makefile +++ /dev/null @@ -1,8 +0,0 @@ - -all: - ghdl -i *.vhd - ghdl -m tb_UART_TX_8N1 - ghdl -r tb_UART_TX_8N1 --stop-time=200us --wave=TX.ghw - -view: - gtkwave TX.ghw diff --git a/doc/using/UART_srcs/tx/path6054.png b/doc/using/UART_srcs/tx/path6054.png Binary files differdeleted file mode 100644 index d2c657243..000000000 --- a/doc/using/UART_srcs/tx/path6054.png +++ /dev/null diff --git a/doc/using/UART_srcs/tx/tb_UART_TX_8N1.vhd b/doc/using/UART_srcs/tx/tb_UART_TX_8N1.vhd deleted file mode 100644 index a485a404a..000000000 --- a/doc/using/UART_srcs/tx/tb_UART_TX_8N1.vhd +++ /dev/null @@ -1,95 +0,0 @@ --- tb_UART_TX_8N1.vhd ----------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity tb_UART_TX_8N1 is -end tb_UART_TX_8N1; - -architecture behavior of tb_UART_TX_8N1 is - - --Inputs - signal board_clk : std_logic := '0'; - signal reset : std_logic := '0'; - signal send_data : std_logic_vector (7 downto 0); - signal wr : std_logic := '0'; - signal tx : std_logic; - - -- Component Declaration for the Unit Under Test (UUT) - component UART_8N1_TX is - generic( - clk_freq : integer; - baudrate : integer; - addr_depth : integer:=5); - port( - clk : in std_logic; - reset : in std_logic; - --8bit interface - wdata : in std_logic_vector(7 downto 0); - wr : in std_logic; - wr_en : out std_logic; - - --physical wire - tx : out std_logic); -end component; - - constant board_clk_period : time := 10 ns; - constant board_clk_freq: integer :=100E6; --100MHz - -begin - - -- Instantiate the Unit Under Test (UUT) -UART_TX: UART_8N1_TX - generic map( - clk_freq => board_clk_freq, - baudrate => 115200 - -- addr_depth => use predefined - ) - port map( - clk => board_clk, - reset => reset, - - wdata => send_data, - wr => wr, - wr_en => open, - - tx => tx - ); - - -- Clock process definitions - board_clk_process : process - begin - board_clk <= '0'; - wait for board_clk_period/2; - board_clk <= '1'; - wait for board_clk_period/2; - end process; - - - -- Stimulus process - stim_proc : process - begin - reset <= '1'; - - wait for 15 us; - reset <='0'; - send_data<=X"A0"; - wait until rising_edge(board_clk); - wr<= '1'; - - wait until rising_edge(board_clk); - wr<= '0'; - - wait for 5 us; - - wait until rising_edge(board_clk); - wr<= '1'; - send_data<=X"B1"; - - wait until rising_edge(board_clk); - wr<= '0'; - wait; - end process; - - end; diff --git a/doc/using/UART_srcs/tx/tx.gtkw b/doc/using/UART_srcs/tx/tx.gtkw deleted file mode 100644 index 92e8cd730..000000000 --- a/doc/using/UART_srcs/tx/tx.gtkw +++ /dev/null @@ -1,33 +0,0 @@ -[*] -[*] GTKWave Analyzer v3.3.67 (w)1999-2015 BSI -[*] Fri Dec 16 19:12:23 2016 -[*] -[dumpfile] "/home/red/artikel_uart/tx/TX.ghw" -[dumpfile_mtime] "Fri Dec 16 19:08:11 2016" -[dumpfile_size] 349946 -[savefile] "/home/red/artikel_uart/tx/tx.gtkw" -[timestart] 0 -[size] 1920 1016 -[pos] -83 -83 -*-35.000000 106965000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] top. -[treeopen] top.tb_uart_tx_8n1. -[treeopen] top.tb_uart_tx_8n1.uart_tx. -[sst_width] 218 -[signals_width] 142 -[sst_expanded] 1 -[sst_vpaned_height] 215 -@28 -top.tb_uart_tx_8n1.board_clk -top.tb_uart_tx_8n1.reset -[color] 5 -top.tb_uart_tx_8n1.wr -@22 -#{top.tb_uart_tx_8n1.send_data[7:0]} top.tb_uart_tx_8n1.send_data[7] top.tb_uart_tx_8n1.send_data[6] top.tb_uart_tx_8n1.send_data[5] top.tb_uart_tx_8n1.send_data[4] top.tb_uart_tx_8n1.send_data[3] top.tb_uart_tx_8n1.send_data[2] top.tb_uart_tx_8n1.send_data[1] top.tb_uart_tx_8n1.send_data[0] -@200 --FIFO_Control -@22 -#{top.tb_uart_tx_8n1.uart_tx.nextread[4:0]} top.tb_uart_tx_8n1.uart_tx.nextread[4] top.tb_uart_tx_8n1.uart_tx.nextread[3] top.tb_uart_tx_8n1.uart_tx.nextread[2] top.tb_uart_tx_8n1.uart_tx.nextread[1] top.tb_uart_tx_8n1.uart_tx.nextread[0] -#{top.tb_uart_tx_8n1.uart_tx.nextwrite[4:0]} top.tb_uart_tx_8n1.uart_tx.nextwrite[4] top.tb_uart_tx_8n1.uart_tx.nextwrite[3] top.tb_uart_tx_8n1.uart_tx.nextwrite[2] top.tb_uart_tx_8n1.uart_tx.nextwrite[1] top.tb_uart_tx_8n1.uart_tx.nextwrite[0] -[pattern_trace] 1 -[pattern_trace] 0 diff --git a/doc/using/UART_srcs/uart.aux b/doc/using/UART_srcs/uart.aux deleted file mode 100644 index d5ba29b80..000000000 --- a/doc/using/UART_srcs/uart.aux +++ /dev/null @@ -1,48 +0,0 @@ -\relax -\providecommand\hyper@newdestlabel[2]{} -\providecommand\HyperFirstAtBeginDocument{\AtBeginDocument} -\HyperFirstAtBeginDocument{\ifx\hyper@anchor\@undefined -\global\let\oldcontentsline\contentsline -\gdef\contentsline#1#2#3#4{\oldcontentsline{#1}{#2}{#3}} -\global\let\oldnewlabel\newlabel -\gdef\newlabel#1#2{\newlabelxx{#1}#2} -\gdef\newlabelxx#1#2#3#4#5#6{\oldnewlabel{#1}{{#2}{#3}}} -\AtEndDocument{\ifx\hyper@anchor\@undefined -\let\contentsline\oldcontentsline -\let\newlabel\oldnewlabel -\fi} -\fi} -\global\let\hyper@last\relax -\gdef\HyperFirstAtBeginDocument#1{#1} -\providecommand\HyField@AuxAddToFields[1]{} -\providecommand\HyField@AuxAddToCoFields[2]{} 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-\BOOKMARK [1][-]{section.2}{advanced TX Unit with FIFO}{}% 2 -\BOOKMARK [1][-]{section.3}{advanced RX Unit with FIFO}{}% 3 -\BOOKMARK [1][-]{section.4}{example application}{}% 4 -\BOOKMARK [1][-]{section.5}{Makefile for workflow}{}% 5 -\BOOKMARK [1][-]{section.6}{file in/out}{}% 6 -\BOOKMARK [1][-]{section.7}{VHPI Interface to an other language}{}% 7 -\BOOKMARK [1][-]{section.8}{closing words}{}% 8 diff --git a/doc/using/UART_srcs/uart.tex b/doc/using/UART_srcs/uart.tex deleted file mode 100644 index 1c1f21e20..000000000 --- a/doc/using/UART_srcs/uart.tex +++ /dev/null @@ -1,269 +0,0 @@ -\documentclass[a4paper,11pt]{article} -\usepackage[T1]{fontenc} -\usepackage[utf8]{inputenc} -\usepackage{lmodern} -%\usepackage{ngerman} -\usepackage{graphicx} -\usepackage{float} -\usepackage{attachfile} -\usepackage[T1]{fontenc} -%\usepackage{beramono}% monospaced font with bold variant - -\usepackage{listings} -\lstdefinelanguage{VHDL}{ - morekeywords={ - library,use,all,entity,is,port,in,out,end,architecture,of, - begin,and,generic,process,if,then,elsif,else,when, - signal, integer,std_logic,unsigned,signed,std_logic_vector, - constant, variable, wait, for, until, map - }, - morecomment=[l]-- -} - -\usepackage{xcolor} -\colorlet{keyword}{blue!100!black!80} -\colorlet{comment}{green!90!black!90} -\lstdefinestyle{vhdl}{ - language = VHDL, - basicstyle = \ttfamily\scriptsize, - keywordstyle = \color{keyword}\bfseries, - commentstyle = \color{comment} -} - -\lstdefinestyle{c}{ - language = c, - basicstyle = \ttfamily\scriptsize, - keywordstyle = \color{keyword}\bfseries, - commentstyle = \color{comment} -} - -\usepackage{hyperref} %remove the red boxes at contents -\hypersetup{colorlinks=true,linkcolor=black} - -\usepackage{fancyvrb} - -\setlength{\parindent}{0em} - - -\title{How to simulate an UART VHDL code with ghdl} -\author{René Doß \\ info@dossmatik.de} - -\begin{document} - -\maketitle -\tableofcontents - -\begin{abstract} -This article was written to demonstrate on a practical example how ghdl works. The reader should have basic knowledge about VHDL. This example is fitable code into a FPGA. The code is written vendor independent. UART as example is generally understandable and also parctical on many applications. -An asynchronous serial transmission has two parts Receiver and Transmitter. The handling is typical integrated on all microcontrollers today. Different sensors can communicate over UART. This makes this data transmission very interesting for a hardware developer. The Receiver and Transmitter code is included with an integrated FIFO. These all are demonstrated with ghdl simulation. You will get new spirit for VHDL code validation. The VHDL files are attached in this document. -\end{abstract} - -\newpage -\section{introduction UART transmission} -The signal is at silence condition high. A low on line manifests a start of transmission, followed by a number of data bits. The data bits are send from least significant bit (LSB) to most significant bit (MSB). Next bit is a high, witch is called stop bit and it is needed to mark the end of transmission. In this state a new start bit can be correct capture by the receiver. Note that no clock signal has sent through the serial line. The transmitter resynchronize on the falling edge in start bit condition. The data speed and the data length of sender an receiver have to be the same. -\begin{figure}[H] - \begin{center} - \includegraphics[scale=0.5]{UART_timing.png} - \caption{UART Timing} - \label{fig:UART Timing} - \end{center} -\end{figure} - -The baudrate specifies the transmission speed. The unit is baud bit per second. Common baudrates are established. -Internally the hardware of UART runs in higher clock rate. - -\section{advanced TX Unit with FIFO} -The UART interface is slow and needs a buffer for better synchronisation. Data is written in a FIFO. FIFO is the abrivation first in first out. This FIFO is realised in a ring buffer. Figure \ref{fig:FIFO pointer} explains how it works. Two pointers point at an address of internal RAM. The pointer nextwrite points to the address where the next incoming data will be written. When new data is incoming the FIFO the pointer is increased. Now valid data has to be read from the FIFO and the nextread is increased. If the two pointers in the FIFO are equal the FIFO is empty. - -\begin{figure}[H] - \begin{center} - \includegraphics[scale=0.5]{tx/BlockTX.png} - \caption{Blockdiagram TX} - \label{fig:Blockdiagram} - \end{center} -\end{figure} -\hrule -\lstinputlisting[style=vhdl]{tx/UART_TX_8N1.vhd} -\hrule -\vspace{10pt} -\begin{figure}[H] - \begin{center} - \includegraphics[scale=0.4]{tx/path6054.png} - \caption{FIFO pointer} - \label{fig:FIFO pointer} - \end{center} -\end{figure} - The FIFO is a circular buffer and works with two address pointers. One pointer is used to point at the write address. The other pointer points at the read address. Both pointers are increased with one step. The interface has two control signals for handshakes. send\_busy and send\_empty these are the FIFO states full and empty. The distance between nextwrite and nextread generates the signal busy because even one more wirte action would cause an overflow in the buffer. - The testbench is required. -\\ -\hrule -\lstinputlisting[style=vhdl]{tx/tb_UART_TX_8N1.vhd} -\hrule -\vspace{10pt} -Put both files in the same directory and simulate this testcase and check the timing requirements. - -\begin{verbatim} -ghdl -i *.vhd -ghdl -m tb_UART_TX_8N1 -ghdl -r tb_UART_TX_8N1 --stop-time=200us --wave=TX.ghw -gtkwave TX.ghw -\end{verbatim} - -\begin{figure}[H] - \begin{center} - \includegraphics[scale=0.3]{tx/TX_simple.png} - \caption{UART TX output} - \end{center} -\end{figure} - -\section{advanced RX Unit with FIFO} -The receiver is the opposite component of the transmitter. The code is mapped also in this article. The generic is used to set the right timing. The tick\_counter is the timer of one bit. The counter range of tick is calculated by the generic clk\_freq and baudrate. These parameters make the code portable into different designs. There is nothing to change inside the code when another frequency or baudrate are used. Such parameter makes source code simpiler reusable. When the transmission is off, the RX has a high on line. The state maschine is in idle and waits for RX to turn low. This condition is checked of the falling edge on the start bit. All other bits are cought in the middle of the bit time. -\\ -\hrule -\lstinputlisting[style=vhdl]{rx/UART_RX_8N1.vhd} -\hrule -\vspace{10pt} -Now the apposite testbench. -\hrule -\lstinputlisting[style=vhdl]{rx/tb_UART_RX_8N1.vhd} -\hrule -\vspace{10pt} - -\begin{verbatim} -ghdl -i *.vhd -ghdl -m tb_UART_RX_8N1 -ghdl -r tb_UART_RX_8N1 --stop-time=800us --wave=RX.ghw -gtkwave RX.ghw -\end{verbatim} - -\begin{figure}[H] - \begin{center} - \includegraphics[scale=0.3]{rx/sim_RX.png} - \caption{UART RX in} - \label{fig:sim RX} - \end{center} -\end{figure} - -\section{example application} -In the last sections we have designed an input and an output interface. By combinating the receiving and transmitting example, we can build the full UART. Now let us make a simple capitalisation ASCII engine. This is more a theoretical example for a demonstration. The data stream is very simple. It demonstrates how it works. -\\ -\hrule -\lstinputlisting[style=vhdl]{capitalisation/capitalisation.vhd} -\hrule -\vspace{10pt} - -The application has an 8bit input and a 8bit output interface. A top instance combine the application and the RX und TX interface together. RX and TX are the physical wires and board\_clk is the internal clock of all. This design is competent to fit inside an FPGA. -\begin{figure}[H] - \begin{center} - \includegraphics[scale=0.4]{capitalisation/zeichnung.png} - \end{center} -\end{figure} - -\hrule -\lstinputlisting[style=vhdl]{capitalisation/top_capitalisation.vhd} -\hrule -\vspace{10pt} -Also for this the testbench. -\\ -\hrule -\lstinputlisting[style=vhdl]{capitalisation/tb_capitalisation.vhd} -\hrule -\vspace{10pt} - -\begin{figure}[H] - \begin{center} - \includegraphics[scale=0.4]{capitalisation/capitalisation.png} - \caption{capitalisation} - \label{fig:capitalisation} - \end{center} -\end{figure} - -\section{Makefile for workflow} -Make is a build tool from the GNU Project. Mostly it is used to control compiling a huge number of files ans solve dependencies. For simplify your life and enhance your productivity you can use is also the make tool to prepair the target in the ghdl simulation. The makefile is like a script with sequential commands. Sometimes rules are insert. If you have larger designs, you should also divide the VHDL design into different files. I use \textbf{make} for this. Store the makefile into the same folder. For run in GHDL type make, this starts all commandos under all. And for view inside the timingdiagram type \textbf{make view}. You find many examples but I give you my makefile for a simple start in GHDL application. -\\ -\hrule -\VerbatimInput{capitalisation/makefile} -\hrule -\vspace{10pt} - - -\section{file in/out} -In former section we had simulate the whole desgin. In larger designs this can be difficult. It needs time to run and it can be also possible some parts are not read. You have to divide the design in moduls and you have to test the moduls by itselfs. Tested moduls can be integated inside the design. The simple 8bit interface is an good standard. Now I show you. How a module can be tested with datas from an file and also put the output into a file. Sometimes is this simpiler to check as a view in a timing diagram. -\begin{figure}[H] - \begin{center} - \includegraphics[scale=0.4]{file_in_out/zeichnung.png} - \end{center} -\end{figure} -The file \textbf{test.txt} is read and the characters goes into the capitalisation and are written in the file \textbf{text1.txt}. - -\vspace{10pt} -\\ -\hrule -\lstinputlisting[style=vhdl]{file_in_out/tb_file.vhd} -\hrule -\vspace{10pt} - -\begin{verbatim} -[test.txt] -Hallo world! Can you see my text? -\end{verbatim} - -\begin{verbatim} -[test1.txt] -HALLO WORLD! CAN YOU SEE MY TEXT? -\end{verbatim} -VHDL has only restricted file operations. It is not possible to seek the fileposition. - -\section{VHPI Interface to an other language} -Here I show one of the highest feature of GHDL. It is possible to link code from another language into the simulation. This can be used for a model or an interface to a real hardware. The possible speed is lower as in an FPGA. For testing is this a change to use mor realistic posibilities. You can data interchange of other programs, for instance testing software. In our case the simulation can communicate with a comport emulator. Linux has pseudoterminals witch is a serial interface in driver lowlever exchange of programs. -First start the c source file. There are only some c functions. -\begin{figure}[H] - \begin{center} - \includegraphics[scale=0.4]{vhpi/zeichnung.png} - \end{center} -\end{figure} -\vspace{10pt} -\\ -\hrule -\lstinputlisting[style=c]{vhpi/tty.c} -\hrule -\vspace{10pt} - -This package is the glue between external code. All c functions get a wrap of a vhdl definition. That makes possible to call a c function in vhdl. This is the advantage of this VHPI interface. -\vspace{10pt} -\hrule -\lstinputlisting[style=vhdl]{vhpi/tty_pkg.vhd} -\hrule -\vspace{10pt} -Also for that case the testbench. -\vspace{10pt} -\\ -\hrule -\lstinputlisting[style=vhdl]{vhpi/tb_tty.vhd} -\hrule -\vspace{10pt} -And the makefile that you can compile and link all together. -\hrule -\VerbatimInput{vhpi/makefile} -\hrule -\vspace{10pt} -In action the simulation prints out the name of the pseudotherminal. I can open a serial terminal program and send datas to the simulation and can also receive the output. - -\begin{figure}[H] - \begin{center} - \includegraphics[scale=0.5]{vhpi/terminal.png} - \end{center} -\end{figure} - -\section{closing words} - The chapter of testbench is very short in the most books. In this article you see the code for testing is adequate to code of application. A simulation is irrecoverable for good results. The development is only effective with simulation. Debug at a later development phase is very difficult. The testbench is the pusher for all effects. The code should also be reusable code. The generic is an interface to set some parameter for a simpler practical integration in the whole application. I hope you could follow all demonstrations and give you idea for better work. - - \begin{verbatim} - the procedure tx_char was posted of Lothar Miller on - http:\\www.mikrocontroller.net - - the VHPI interface for pseudotherminal was posted - of Wojciech M. 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-ENTITY tb_tty IS -END tb_tty; - -ARCHITECTURE behavior OF tb_tty IS - -signal clk : std_logic := '0'; -signal reset : std_logic; - -signal data_in : std_logic_vector(7 downto 0); -signal wdata : std_logic_vector(7 downto 0); -signal wr_en : std_logic:='1'; -signal wr : std_logic; -signal rd_en : std_logic; -signal rd : std_logic; -signal a : integer; -signal c : integer; - - -component capitalisation is - port( - clk : in std_logic; - reset : in std_logic; - --in - rdata : in std_logic_vector(7 downto 0); - rd_en : in std_logic; - rd : out std_logic; - --out - wdata : out std_logic_vector(7 downto 0); - wr_en : in std_logic; - wr : out std_logic - ); -end component; - - -- Clock period definitions - constant clk_period : time := 10 ns; - -subtype by_te is character; -type f_byte is file of by_te; - -BEGIN - ---file open - process - begin c<=tty_open(0); - wait; - end process; - ---read -process (clk) - -variable b: integer; -begin - if rising_edge(CLK) then - a<= read_enable(0); - if a=1 then - data_in<=std_logic_vector(to_unsigned(read_data(0),8)); - rd_en<='1'; - else - rd_en<='0'; - end if; - end if; - -end process; - ---write -process (clk) -variable b: integer; - - begin - if rising_edge(CLK) then - if reset='0' then - if wr='1' then - b:=to_integer(unsigned(wdata)); - write_data(b); - end if; - end if; - end if; - end process; - - stim_proc : process - begin - reset <= '1'; - - wait for 50 ns; - reset <='0'; - wait; - end process; - - clk_process :process - begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - -engine: capitalisation - port map( - clk => clk, - reset => reset, - --in - rdata => data_in, - rd_en => rd_en, - rd => rd, - --out - wdata => wdata, - wr_en => wr_en, - wr => wr - ); -END; diff --git a/doc/using/UART_srcs/vhpi/terminal.png b/doc/using/UART_srcs/vhpi/terminal.png Binary files differdeleted file mode 100644 index a19f3cd64..000000000 --- a/doc/using/UART_srcs/vhpi/terminal.png +++ /dev/null diff --git a/doc/using/UART_srcs/vhpi/tty.c b/doc/using/UART_srcs/vhpi/tty.c deleted file mode 100644 index c04f8f359..000000000 --- a/doc/using/UART_srcs/vhpi/tty.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - VPI code allowing you to connect terminal emulator or other program to pty "connected" - to the UART-like port in IP core simulated in GHDL. - - This code is written by Wojciech M. Zabolotny (wz...@ise.pw.edu.pl) on 2nd June 2011 - and is published as PUBLIC DOMAIN - -*/ - -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <stdarg.h> -#include <unistd.h> -#include <sys/types.h> -#include <sys/ioctl.h> -#include <linux/ioctl.h> -#include <sys/stat.h> -#include <sys/poll.h> -#include <fcntl.h> -#include <errno.h> - -char *ptsname(int fd); - -int ptyf = -1; - - - -int tty_open(int a) -{ - ptyf = open("/dev/ptmx",O_RDWR); - if(ptyf<0) { - perror("I can't open pseudoterminal\n"); - return -1; - } - if(unlockpt(ptyf)<0) { - perror("I can't unlock pseudoterminal\n"); - return -1; - } - if(grantpt(ptyf)<0) { - perror("I can't grant pseudoterminal\n"); - return -1; - } - printf("Pseudoterminal: %s\n",ptsname(ptyf)); - // sleep(10); - return 0; -} - - -int read_enable(void) -{ - //In the masks below you may omit POLLHUP in this case - //disconnection of the terminal emulator from pty will not - //stop simulation, and you'll be able to reconnect - //the same or different program to pty and running simulation - struct pollfd pfd[1]={{ptyf,POLLIN | POLLERR | POLLHUP,0}}; - int res; - res=poll(pfd,1,0); - if(res==0) return 0; - if(res<0) return 0; //error - //If you removed POLLHUP from the mask above, you should remove it below too - if(pfd[0].revents & (POLLERR|POLLHUP)) return 0; //disconnected or error? - if(pfd[0].revents & POLLIN) return 1; - return 0; -} - - -int read_data(void) -{ - unsigned char c; - read(ptyf,&c,1); - return c; -} - -int write_data(int byte) -{ - unsigned char c = byte; - write(ptyf,&c,1); - - // Debug: printf("Writing %x to pty\n", c); - return 0; -} - diff --git a/doc/using/UART_srcs/vhpi/tty_pkg.vhd b/doc/using/UART_srcs/vhpi/tty_pkg.vhd deleted file mode 100644 index 99e3a347f..000000000 --- a/doc/using/UART_srcs/vhpi/tty_pkg.vhd +++ /dev/null @@ -1,70 +0,0 @@ ---tty_pkg.vhd -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package tty_pkg is - - function to_integer( s: std_logic) return integer; - function to_std_logic( s : integer ) return std_logic; - - function tty_open (portn : integer) return integer; - attribute foreign of tty_open : - function is "VHPIDIRECT tty_open"; - - function read_data ( dummy: integer) return integer; - attribute foreign of read_data : - function is "VHPIDIRECT read_data"; - - function read_enable ( dummy: integer) return integer; - attribute foreign of read_enable : - function is "VHPIDIRECT read_enable"; - - procedure write_data ( data: in integer); - attribute foreign of write_data : - procedure is "VHPIDIRECT write_data"; - -end; - - -package body tty_pkg is - - function to_integer( s : std_logic ) return integer is - begin - if s = '1' then - return 1; - else - return 0; - end if; - end function; - - function to_std_logic( s : integer ) return std_logic is - begin - if s > 0 then - return '1'; - else - return '0'; - end if; - end function; - - - function tty_open (portn : integer) return integer is - begin - assert false report "VHPI" severity failure; - end tty_open; - - function read_data (dummy: integer) return integer is - begin - assert false report "VHPI" severity failure; - end read_data; - - function read_enable (dummy: integer) return integer is - begin - assert false report "VHPI" severity failure; - end read_enable; - - procedure write_data ( data: in integer) is - begin - assert false report "VHPI" severity failure; - end write_data; -end tty_pkg; diff --git a/doc/using/UART_srcs/vhpi/zeichnung.png b/doc/using/UART_srcs/vhpi/zeichnung.png Binary files differdeleted file mode 100644 index fbfdec259..000000000 --- a/doc/using/UART_srcs/vhpi/zeichnung.png +++ /dev/null |