From 8e06c39ed8311aeb36696d9f964550407e1c556e Mon Sep 17 00:00:00 2001 From: 1138-4EB <1138-4EB@users.noreply.github.com> Date: Sat, 9 Dec 2017 17:34:58 +0100 Subject: clean todos --- doc/using/QuickStartGuide.rst | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'doc/using/QuickStartGuide.rst') diff --git a/doc/using/QuickStartGuide.rst b/doc/using/QuickStartGuide.rst index b390b382e..a1afa00b2 100644 --- a/doc/using/QuickStartGuide.rst +++ b/doc/using/QuickStartGuide.rst @@ -216,13 +216,3 @@ Unless you are only studying VHDL, you will work with larger designs than the on * Remove the :file:`work/` directory: ``rm -rf work``. Only the executable is kept. If you want to rebuild the design, create the :file:`work/` directory, import the sources, and make the design. .. WARNING:: Sometimes, a design does not fully follow the VHDL standards. For example it uses the badly engineered ``std_logic_unsigned`` package. GHDL supports this VHDL dialect through some options: ``--ieee=synopsys -fexplicit``. See section ':ref:`IEEE_library_pitfalls`', for more details. - -Further examples -======================= - -.. TODO:: - - * Add references to examples/tutorials with GHDL. - * Shall `René Doß ` want to contribute adapting his article to RST? - * https://github.com/Obijuan/open-fpga-verilog-tutorial/wiki ->>>>>>> doc/changelog renamed to doc/appendix -- cgit v1.2.3