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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-25 05:33:09 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-25 05:33:09 +0200 |
| commit | fe4cf1f80f6c805e629e6909d259d17a915b05e3 (patch) | |
| tree | 183a44b3a2f229dc7c61014f34aa04fe165678bf | |
| parent | 554256d7fc71430610ed34eee3e3df92ff9be871 (diff) | |
| download | ghdl-fe4cf1f80f6c805e629e6909d259d17a915b05e3.tar.gz ghdl-fe4cf1f80f6c805e629e6909d259d17a915b05e3.tar.bz2 ghdl-fe4cf1f80f6c805e629e6909d259d17a915b05e3.zip | |
synth: fix incorrect slice in disp_vhdl for Insert.
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index cb02c49ca..08ab63a94 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -484,12 +484,7 @@ package body Netlists.Disp_Vhdl is Disp_Template ("\i0 (\n0 downto \n1) & ", Inst, (0 => Ow - 1, 1 => Off + Iw)); end if; - if Iw > 1 then - Disp_Template ("\i1 (\n0 downto \n1)", Inst, - (0 => Off + Iw - 1, 1 => Off)); - else - Disp_Template ("\i1", Inst); - end if; + Disp_Template ("\i1", Inst); if Off > 1 then Disp_Template (" & \i0 (\n0 downto 0)", Inst, (0 => Off - 1)); |