From fe4cf1f80f6c805e629e6909d259d17a915b05e3 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 25 Jul 2019 05:33:09 +0200
Subject: synth: fix incorrect slice in disp_vhdl for Insert.

---
 src/synth/netlists-disp_vhdl.adb | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index cb02c49ca..08ab63a94 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -484,12 +484,7 @@ package body Netlists.Disp_Vhdl is
                   Disp_Template ("\i0 (\n0 downto \n1) & ", Inst,
                                  (0 => Ow - 1, 1 => Off + Iw));
                end if;
-               if Iw > 1 then
-                  Disp_Template ("\i1 (\n0 downto \n1)", Inst,
-                                 (0 => Off + Iw - 1, 1 => Off));
-               else
-                  Disp_Template ("\i1", Inst);
-               end if;
+               Disp_Template ("\i1", Inst);
                if Off > 1 then
                   Disp_Template (" & \i0 (\n0 downto 0)", Inst,
                                  (0 => Off - 1));
-- 
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