testsuite/synth: improve test comp04

4 files changed, 89 insertions, 9 deletions

diff --git a/testsuite/synth/comp04/tb_comp04.vhdl b/testsuite/synth/comp04/tb_comp04.vhdl
new file mode 100644
index 000000000..d9a9de54a
--- /dev/null
+++ b/testsuite/synth/comp04/tb_comp04.vhdl
@@ -0,0 +1,28 @@
+entity tb_comp04 is
+end tb_comp04;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_comp04 is
+  signal v : std_logic_vector (7 downto 0);
+  signal r : std_logic_vector (7 downto 0);
+begin
+  comp04_1: entity work.comp04
+    port map (
+      v => v,
+      r => r);
+
+  process
+  begin
+    v <= b"1100_0011";
+    wait for 1 ns;
+    assert r = b"1100_0011" severity failure;
+
+    v <= b"1100_0010";
+    wait for 1 ns;
+    assert r = b"0000_0000" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/comp04/tb_comp05.vhdl b/testsuite/synth/comp04/tb_comp05.vhdl
new file mode 100644
index 000000000..d2f3ad402
--- /dev/null
+++ b/testsuite/synth/comp04/tb_comp05.vhdl
@@ -0,0 +1,28 @@
+entity tb_comp05 is
+end tb_comp05;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_comp05 is
+  signal v : std_logic_vector (7 downto 0);
+  signal r : std_logic_vector (7 downto 0);
+begin
+  comp05_1: entity work.comp05
+    port map (
+      v => v,
+      r => r);
+
+  process
+  begin
+    v <= b"1100_0011";
+    wait for 1 ns;
+    assert r = b"0011_1100" severity failure;
+
+    v <= b"1100_0010";
+    wait for 1 ns;
+    assert r = b"0011_1101" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/comp04/tb_comp06.vhdl b/testsuite/synth/comp04/tb_comp06.vhdl
new file mode 100644
index 000000000..8320e3281
--- /dev/null
+++ b/testsuite/synth/comp04/tb_comp06.vhdl
@@ -0,0 +1,28 @@
+entity tb_comp06 is
+end tb_comp06;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_comp06 is
+  signal v : std_logic_vector (7 downto 0);
+  signal r : std_logic_vector (7 downto 0);
+begin
+  comp06_1: entity work.comp06
+    port map (
+      v => v,
+      r => r);
+
+  process
+  begin
+    v <= x"0f";
+    wait for 1 ns;
+    assert r = x"0c" severity failure;
+
+    v <= x"f0";
+    wait for 1 ns;
+    assert r = x"70" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/comp04/testsuite.sh b/testsuite/synth/comp04/testsuite.sh
index b7974d5a7..5b18ae376 100755
--- a/testsuite/synth/comp04/testsuite.sh
+++ b/testsuite/synth/comp04/testsuite.sh
@@ -2,15 +2,11 @@
 
 . ../../testenv.sh
 
-for t in comp04 comp05 comp06; do
-#    analyze $t.vhdl tb_$t.vhdl
-#    elab_simulate tb_$t
-#    clean
-
-    synth $t.vhdl -e $t > syn_$t.vhdl
-    analyze syn_$t.vhdl #tb_$t.vhdl
-#    elab_simulate tb_$t --ieee-asserts=disable-at-0
-    clean
+for keep in yes no; do
+    GHDL_SYNTH_FLAGS=--keep-hierarchy=$keep
+    for unit in comp04 comp05 comp06; do
+	synth_tb $unit
+    done
 done
 
 echo "Test successful"