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-rw-r--r--testsuite/synth/comp04/tb_comp06.vhdl28
1 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/synth/comp04/tb_comp06.vhdl b/testsuite/synth/comp04/tb_comp06.vhdl
new file mode 100644
index 000000000..8320e3281
--- /dev/null
+++ b/testsuite/synth/comp04/tb_comp06.vhdl
@@ -0,0 +1,28 @@
+entity tb_comp06 is
+end tb_comp06;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_comp06 is
+ signal v : std_logic_vector (7 downto 0);
+ signal r : std_logic_vector (7 downto 0);
+begin
+ comp06_1: entity work.comp06
+ port map (
+ v => v,
+ r => r);
+
+ process
+ begin
+ v <= x"0f";
+ wait for 1 ns;
+ assert r = x"0c" severity failure;
+
+ v <= x"f0";
+ wait for 1 ns;
+ assert r = x"70" severity failure;
+
+ wait;
+ end process;
+end behav;