diff options
| author | Tristan Gingold <tgingold@free.fr> | 2023-04-19 18:48:02 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-04-19 20:55:57 +0200 |
| commit | 98b8ea7d96a7dabe04cac48fd4e2cf2e7f5a05dd (patch) | |
| tree | 5e59ed650e8fab673dfa2afffe2ff4c58bd6b113 | |
| parent | cc5cf36c2d2e87eaf01b608c7391abdba8f9fff7 (diff) | |
| download | ghdl-98b8ea7d96a7dabe04cac48fd4e2cf2e7f5a05dd.tar.gz ghdl-98b8ea7d96a7dabe04cac48fd4e2cf2e7f5a05dd.tar.bz2 ghdl-98b8ea7d96a7dabe04cac48fd4e2cf2e7f5a05dd.zip | |
ghdlsynth: add --keep-hierarchy option
| -rw-r--r-- | src/ghdldrv/ghdlsynth.adb | 44 |
1 files changed, 30 insertions, 14 deletions
diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb index 6e2871afa..e44c06993 100644 --- a/src/ghdldrv/ghdlsynth.adb +++ b/src/ghdldrv/ghdlsynth.adb @@ -173,6 +173,17 @@ package body Ghdlsynth is Cmd.Top_Encoding := Name_Hash; elsif Option = "--top-name=asis" then Cmd.Top_Encoding := Name_Asis; + elsif Option'Last >= 16 and then Option (1 .. 16) = "--keep-hierarchy" + then + if Option'Last = 16 + or else Option (17 .. Option'Last) = "=yes" + then + Synth.Flags.Flag_Keep_Hierarchy := True; + elsif Option (17 .. Option'Last) = "=no" then + Synth.Flags.Flag_Keep_Hierarchy := False; + else + Res := Option_Unknown; + end if; elsif Option'Last > 17 and then Option (1 .. 17) = "--vendor-library=" then @@ -201,20 +212,25 @@ package body Ghdlsynth is Cmd.Disp_Inline := False; elsif Option = "--disp-noid" then Cmd.Disp_Id := False; - elsif Option = "--out=raw" then - Cmd.Oformat := Format_Raw; - elsif Option = "--out=dump" then - Cmd.Oformat := Format_Dump; - elsif Option = "--out=dot" then - Cmd.Oformat := Format_Dot; - elsif Option = "--out=none" then - Cmd.Oformat := Format_None; - elsif Option = "--out=vhdl" then - Cmd.Oformat := Format_Vhdl; - elsif Option = "--out=raw-vhdl" then - Cmd.Oformat := Format_Raw_Vhdl; - elsif Option = "--out=verilog" then - Cmd.Oformat := Format_Verilog; + elsif Option'Length > 6 and then Option (1 .. 6) = "--out=" then + if Option (7 .. Option'Last) = "raw" then + Cmd.Oformat := Format_Raw; + elsif Option (7 .. Option'Last) = "dump" then + Cmd.Oformat := Format_Dump; + elsif Option (7 .. Option'Last) = "dot" then + Cmd.Oformat := Format_Dot; + elsif Option (7 .. Option'Last) = "none" then + Cmd.Oformat := Format_None; + elsif Option (7 .. Option'Last) = "vhdl" then + Cmd.Oformat := Format_Vhdl; + elsif Option (7 .. Option'Last) = "raw-vhdl" then + Cmd.Oformat := Format_Raw_Vhdl; + elsif Option (7 .. Option'Last) = "verilog" then + Cmd.Oformat := Format_Verilog; + else + Res := Option_Unknown; + end if; + return; elsif Option = "-di" then Flag_Debug_Noinference := True; elsif Option = "-dc" then |