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author | Tristan Gingold <tgingold@free.fr> | 2022-01-11 19:39:05 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-01-12 08:30:18 +0100 |
commit | 4b97bbb1830f10ec17e07c5d312e35a83019a9ce (patch) | |
tree | 1fcf531958528e80bd6403b25a59c168aec87e83 | |
parent | 82bc056875df996138ffa54b89f52663dfb17f1a (diff) | |
download | ghdl-4b97bbb1830f10ec17e07c5d312e35a83019a9ce.tar.gz ghdl-4b97bbb1830f10ec17e07c5d312e35a83019a9ce.tar.bz2 ghdl-4b97bbb1830f10ec17e07c5d312e35a83019a9ce.zip |
testsuite/synth: add a test for #1945
-rw-r--r-- | testsuite/synth/issue1945/alias01.vhdl | 16 | ||||
-rw-r--r-- | testsuite/synth/issue1945/alias02.vhdl | 20 | ||||
-rw-r--r-- | testsuite/synth/issue1945/mwe.vhdl | 29 | ||||
-rw-r--r-- | testsuite/synth/issue1945/tb_alias01.vhdl | 26 | ||||
-rw-r--r-- | testsuite/synth/issue1945/tb_alias02.vhdl | 26 | ||||
-rwxr-xr-x | testsuite/synth/issue1945/testsuite.sh | 11 |
6 files changed, 128 insertions, 0 deletions
diff --git a/testsuite/synth/issue1945/alias01.vhdl b/testsuite/synth/issue1945/alias01.vhdl new file mode 100644 index 000000000..89bf24b6b --- /dev/null +++ b/testsuite/synth/issue1945/alias01.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.STD_LOGIC_1164.all; + +entity alias01 is + port( + i : in std_logic_vector(7 downto 0); + o : out std_logic + ); +end entity; + +architecture rtl of alias01 is + alias i_alias : std_logic_vector(7 downto 2) is i(6 downto 1); + alias lower : std_logic_vector(3 downto 0) is i_alias(6 downto 3); +begin + o <= '1' when lower = "0000" else '0'; +end architecture; diff --git a/testsuite/synth/issue1945/alias02.vhdl b/testsuite/synth/issue1945/alias02.vhdl new file mode 100644 index 000000000..010ed01c3 --- /dev/null +++ b/testsuite/synth/issue1945/alias02.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.STD_LOGIC_1164.all; + +entity alias02 is + port( + i : in std_logic; + o : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture rtl of alias02 is + alias o_alias : std_logic_vector(7 downto 2) is o(6 downto 1); + alias o_alias2 : std_logic_vector(3 downto 0) is o_alias(6 downto 3); +begin + o (7) <= '1'; + o (0) <= '1'; + o_alias (7) <= '1'; + o_alias (2) <= '1'; + o_alias2 <= i & i & i & i; +end architecture; diff --git a/testsuite/synth/issue1945/mwe.vhdl b/testsuite/synth/issue1945/mwe.vhdl new file mode 100644 index 000000000..9bfe5d8f2 --- /dev/null +++ b/testsuite/synth/issue1945/mwe.vhdl @@ -0,0 +1,29 @@ +library ieee; +use ieee.STD_LOGIC_1164.all; + +entity MWE is + port( + i : in std_logic_vector(7 downto 0); + o : out std_logic + ); +end entity; + +architecture rtl of MWE is + alias i_alias : std_logic_vector(7 downto 0) is i; + -- this crashes: + alias lower : std_logic_vector(3 downto 0) is i_alias(3 downto 0); + -- this works fine: + -- alias lower : std_logic_vector(3 downto 0) is i(3 downto 0); +begin + -- this works fine too: + -- o <= '1' when lower(3 downto 0) = "0000" else '0'; + + process(all) + begin + if lower = "0000" then + o <= '1'; + else + o <= '0'; + end if; + end process; +end architecture; diff --git a/testsuite/synth/issue1945/tb_alias01.vhdl b/testsuite/synth/issue1945/tb_alias01.vhdl new file mode 100644 index 000000000..905a67a48 --- /dev/null +++ b/testsuite/synth/issue1945/tb_alias01.vhdl @@ -0,0 +1,26 @@ +entity tb_alias01 is +end tb_alias01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_alias01 is + signal i : std_logic_vector(7 downto 0); + signal o : std_logic; +begin + dut: entity work.alias01 + port map (i, o); + + process + begin + i <= "11000011"; + wait for 1 ns; + assert o = '1' severity failure; + + i <= "11100011"; + wait for 1 ns; + assert o = '0' severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1945/tb_alias02.vhdl b/testsuite/synth/issue1945/tb_alias02.vhdl new file mode 100644 index 000000000..ccc2ee17f --- /dev/null +++ b/testsuite/synth/issue1945/tb_alias02.vhdl @@ -0,0 +1,26 @@ +entity tb_alias02 is +end tb_alias02; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_alias02 is + signal o : std_logic_vector(7 downto 0); + signal i : std_logic; +begin + dut: entity work.alias02 + port map (i => i, o => o); + + process + begin + i <= '1'; + wait for 1 ns; + assert o = x"ff" severity failure; + + i <= '0'; + wait for 1 ns; + assert o = x"c3" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1945/testsuite.sh b/testsuite/synth/issue1945/testsuite.sh new file mode 100755 index 000000000..8c4947113 --- /dev/null +++ b/testsuite/synth/issue1945/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_only mwe + +synth_tb alias01 +synth_tb alias02 + +echo "Test successful" |