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author | Tristan Gingold <tgingold@free.fr> | 2022-01-11 19:38:44 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-01-12 08:30:17 +0100 |
commit | 82bc056875df996138ffa54b89f52663dfb17f1a (patch) | |
tree | 7da466fec30b884409fd58834072430e906ad6fc | |
parent | 6af4fb0c53fa0c57f14f07d54f8d32b58c4a1b2a (diff) | |
download | ghdl-82bc056875df996138ffa54b89f52663dfb17f1a.tar.gz ghdl-82bc056875df996138ffa54b89f52663dfb17f1a.tar.bz2 ghdl-82bc056875df996138ffa54b89f52663dfb17f1a.zip |
synth: handle alias of alias. Fix #1945
-rw-r--r-- | src/synth/synth-vhdl_decls.adb | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/src/synth/synth-vhdl_decls.adb b/src/synth/synth-vhdl_decls.adb index ae320e6cc..5eefbdaef 100644 --- a/src/synth/synth-vhdl_decls.adb +++ b/src/synth/synth-vhdl_decls.adb @@ -502,6 +502,7 @@ package body Synth.Vhdl_Decls is Aval : Valtyp; Obj : Value_Acc; Base : Node; + Off : Uns32; begin Val := Get_Value (Syn_Inst, Decl); pragma Assert (Val.Val.Kind = Value_Alias); @@ -509,15 +510,27 @@ package body Synth.Vhdl_Decls is if Obj.Kind = Value_Signal then -- A signal must have been changed to a wire or a net, but the -- aliases have not been updated. Update here. - Base := Get_Base_Name (Get_Name (Decl)); + Base := Decl; + loop + Base := Get_Base_Name (Get_Name (Base)); + exit when Get_Kind (Base) /= Iir_Kind_Object_Alias_Declaration; + end loop; + Aval := Synth_Expression (Syn_Inst, Base); + Off := Val.Val.A_Off.Net_Off; + + -- Handle alias of alias here. + if Aval.Val.Kind = Value_Alias then + Aval := (Aval.Val.A_Typ, Aval.Val.A_Obj); + end if; + if Aval.Val.Kind = Value_Net then -- Object is a net if it is not writable. Extract the -- bits for the alias. Aval := Create_Value_Net (Build2_Extract (Get_Build (Syn_Inst), Get_Value_Net (Aval.Val), - Val.Val.A_Off.Net_Off, Val.Typ.W), + Off, Val.Typ.W), Val.Typ); Val.Val.A_Off := (0, 0); end if; |