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-rw-r--r--testsuite/synth/issue1909/reproducebug.vhdl6
1 files changed, 3 insertions, 3 deletions
diff --git a/testsuite/synth/issue1909/reproducebug.vhdl b/testsuite/synth/issue1909/reproducebug.vhdl
index 60655b0eb..940ca41ce 100644
--- a/testsuite/synth/issue1909/reproducebug.vhdl
+++ b/testsuite/synth/issue1909/reproducebug.vhdl
@@ -5,8 +5,8 @@ library ieee;
entity ReproduceBug is
port(
clk : in std_logic;
- input : in unsigned(7 downto 0);
- output : out unsigned(7 downto 0)
+ inp : in unsigned(7 downto 0);
+ outp : out unsigned(7 downto 0)
);
end ReproduceBug;
@@ -18,7 +18,7 @@ begin
Main: process(clk)
begin
if rising_edge(Clk) then
- output <= input ror 1; -- can also be 'rol'
+ outp <= inp ror 1; -- can also be 'rol'
end if;
end process;