aboutsummaryrefslogtreecommitdiffstats
path: root/testsuite/issues/issue73/multi.vhdl
diff options
context:
space:
mode:
authorTristan Gingold <tgingold@free.fr>2019-12-05 22:32:49 +0100
committerTristan Gingold <tgingold@free.fr>2019-12-05 22:32:49 +0100
commit0833d3f90a29f0bce364833f20430968deeee0b7 (patch)
tree4f91c24c02956fe435de2c079258cc76eb7324b0 /testsuite/issues/issue73/multi.vhdl
parent41222e9d1193dedc407158352f7180dc6d5ee655 (diff)
downloadghdl-yosys-plugin-0833d3f90a29f0bce364833f20430968deeee0b7.tar.gz
ghdl-yosys-plugin-0833d3f90a29f0bce364833f20430968deeee0b7.tar.bz2
ghdl-yosys-plugin-0833d3f90a29f0bce364833f20430968deeee0b7.zip
Add testcase for #73
Diffstat (limited to 'testsuite/issues/issue73/multi.vhdl')
-rw-r--r--testsuite/issues/issue73/multi.vhdl27
1 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/issues/issue73/multi.vhdl b/testsuite/issues/issue73/multi.vhdl
new file mode 100644
index 0000000..3255b26
--- /dev/null
+++ b/testsuite/issues/issue73/multi.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cell1 is
+ port (
+ O: out std_logic
+ );
+end entity cell1;
+
+architecture rtl of cell1 is
+begin
+ O <= '0';
+end architecture rtl;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cell2 is
+ port (
+ O: out std_logic
+ );
+end entity cell2;
+
+architecture rtl of cell2 is
+begin
+ O <= '1';
+end architecture rtl;