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* Global cleanup: Fix a few spelling errorsMartin Roth2022-05-031-1/+1
| | | | | | | | | | | | | | | | Just a trivial patch to fix a few errors found by codespell. Here's the command I used: codespell -S subprojects,out \ -L fwe,dout,tast,crate,parms,claus,nt,nd,te,truns,trun Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4e3b277f220fa70dcab21912c30f1d26d9bd8749 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62840 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Introduce HSFC CYCLE READ/WRITE/ERASE macrosSubrata Banik2022-05-031-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces useful macros (read/write/erase) and uses these macros throughout the SPI operations. Additionally, implicitly using the HSFC_CYCLE_READ macro for the SPI read operation. BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Additionally, no difference in flashrom binary seen while comparing flashrom binary generated with CB:62888 and between CB:62888 to CB:62868 below: flashrom$ cmp flashrom flashrom_old <<none>> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3ea74b668e5f8d8e4b3da2a8ad8b81f1813e1e80 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62868 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Introduce HSFC_FDBC_VAL(n) macroSubrata Banik2022-05-031-2/+3
| | | | | | | | | | | | | | | This patch introduces HSFC_FDBC_VAL(n) macro to use in SPI read and write operations. BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie2512c85de9fc21286234b97f5842ecef1729787 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ichspi: Introduce HSFC_FCYCLE_MASK(n) macroSubrata Banik2022-05-031-2/+21
| | | | | | | | | | | | | | | This patch introduces HSFC_FCYCLE_MASK(n) macro to cover both ICH and PCH hardware sequencing FCYCLE Bit width. BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id222304165610c7ae48e365d72ec8fdeea51c51d Reviewed-on: https://review.coreboot.org/c/flashrom/+/62891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ichspi: Drop unused `_pprint_reg` macroSubrata Banik2022-05-031-2/+1
| | | | | | | | | | | | | | | | | | | | | | | This patch drops `_pprint_reg` macro as `pprint_reg` macro is now able to call into msg_pdbg(). BUG=b:223630977 TEST=Able to display HSFS register offset properly as below BIOS_CNTL = 0x8b: BIOS Lock Enable: enabled, BIOS Write Enable: enabled Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. SPIBAR = 0x00007fce5a270000 (phys = 0xfe010000) 0x04: 0xf000 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iee7a23447de38423b61008b3242d28ce553ae0a2 Reviewed-on: https://review.coreboot.org/c/flashrom/+/63549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* ichspi: Use `pprint_reg` macro for PCH100 HSFC FCYCLE offsetSubrata Banik2022-05-031-1/+1
| | | | | | | | | | | | | | | | This patch uses `pprint_reg` macro instead `_pprint_reg` with explicit register name and offset macros being passed as argument. BUG=b:223630977 TEST=Able to display PCH100_HSFC.FCYCLE offset properly. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5a8d84639b7226bf82458a7310f306c5232cffe3 Reviewed-on: https://review.coreboot.org/c/flashrom/+/63470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macrosSubrata Banik2022-05-031-3/+3
| | | | | | | | | | | | | | | | | | | | This patch renames the `WET` macro definitions based on its availability with PCH100 onwards chipset. HSFC_WET_OFF -> PCH100_HSFC_WET_OFF HSFC_WET -> PCH100_HSFC_WET BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f Reviewed-on: https://review.coreboot.org/c/flashrom/+/62888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Unify timeouts across all SPI operations to 30sSubrata Banik2022-04-271-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `ich_hwseq_wait_for_cycle_complete()` drops taking `timeout` as argument in favor of a fixed timeout of `30 seconds` for any given SPI operation as recommended by the SPI programming guide. Document: Alder Lake-P Client Platform SPI Programming Guide Rev 1.30 (supporting document for multi-master accessing the SPI Flash device.) Refer to below section to understand the problem in more detail and SPI operation timeout recommendation from Intel in multi-master scenarios. On Intel Chipsets that support multi-mastering access of the SPI flash may run into a timeout failure when the operation initiated from a single master just follows the SPI operational timeout recommendation as per the vendor datasheet (example: winbond spiflash W25Q256JV-DTR specification, table 9.7). In the multi-master SPI accessing scenario using hardware sequencing operation, it's impossible to know the actual status of the SPI bus prior to individual master starting the operation (SPI Cycle In Progress a.k.a SCIP bit represents the status of SPI operation on individual master). Thus, any SPI operation triggered in multi-master environment might need to account a worst case scenario where the most time consuming operation might have occupied the SPI bus from a master and an operation initiated by another master just timed out. Here is the timeout calculation for any hardware sequencing operation: Worst Case Operational Delay = (Maximum Time consumed by a SPI operation + Any marginal adjustment) Timeout Recommendation for Hardware Sequencing Operation = ((Worst Case Operational Delay) * (#No. Of SPI Master - 1) + Current Operational latency) Assume, on Intel platform with 6 SPI master like, Host CPU, CSE, EC, GbE and other reserved etc, hence, the Timeout Calculation for SPI erase Operation would look like as below: Maximum Time consumed by a SPI Operation = 5 seconds Worst Case Operational Delay = 5 seconds Timeout Recommendation for Hardware Seq Operation = 5 seconds * (6 - 1) + 5 seconds = 30 seconds BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b Reviewed-on: https://review.coreboot.org/c/flashrom/+/62867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ichspi: Add Jasper Lake supportEdward O'Callaghan2022-04-141-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Jasper Lake is the same as Elkhart Lake. BUG=b:221175960 TEST=dedede with `flashrom -p internal --flash-size`. ``` $ flashrom -VVV -p internal --ifd -i fd -i bios -r /tmp/filename.rom <snip> Enabling hardware sequencing by default for 100+ series PCH. OK. No board enable found matching coreboot IDs vendor="Google", model="Magolor". The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Chip identified: GD25Q127C/GD25Q128C Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB. There is only one partition containing the whole address space (0x000000 - 0xffffff). There are 4096 erase blocks with 4096 B each. Added layout entry 00000000 - 00ffffff named complete flash Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading Status register Block protection is disabled. Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset 'Jasper Lake'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00381000 - 00ffffff named bios Added layout entry 00001000 - 00380fff named me restore_power_management: Re-enabling power management. Using regions: "bios", "fd". Reading Status register Block protection is disabled. Reading flash... 0x381000-0xffffff:R Reading 13103104 bytes starting at 0x381000. 000000-0x0fff:R Reading 4096 bytes starting at 0x000000. done. restore_power_management: Re-enabling power management. SUCCESS Restoring PCI config space for 00:1f:5 reg 0xdc restore_power_management: Re-enabling power management. ``` Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sam McNally <sammc@google.com>
* ichspi: Add support for Meteor LakeSubrata Banik2022-03-301-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Meteor Lake support into flashrom. Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Meteor Lake is the same as Elkhart Lake. BUG=b:224325352 TEST=Flashrom is able to detect MTL SPI DID and show chipset name as below: > flashrom --flash-name .... Found chipset "Intel Meteor Lake-P/M". .... > flashrom - internal --ifd -i fd -i bios -r /tmp/bios.rom .... Reading ich_descriptor... done. Assuming chipset 'Meteor Lake'. Using regions: "bios", "fd". Reading flash... done. SUCCESS Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a2ffe2ba8d96c90d89b77e0d8583d179ff02a75 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sam McNally <sammc@google.com>
* ichspi.c: Check SPI Cycle In-Progress prior start HW SeqSubrata Banik2022-03-091-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit. Software must initiate the next SPI transaction when this bit is 0. Platform Setup: Alder Lake based ChromeOS devices (Brya variants) Replication Steps: Accepting and running firmware Auto Update (AU) on the Brya variants (dogfooder system) is seeing `flashrom` getting timed out. Problem Statement: Evidencing AU (Auto Update) failure while performing firmware update on the Alder Lake based ChromeOS devices. Observation: Based on the initial understanding from the failure log/pattern, it seems like the platform is evidencing multiple `flashrom` access from different source, for example: `futility` accesses flashrom for erase, write and read operation, `crossystem` uses flashrom for updating VBNV, additionally, `set_fw_good` script also uses `crossystem` to update the fw status. Solution: Without this SCIP check being implemented in flashrom, there is no way to ensure multiple instances of flashrom performing different SPI operations are not cancelling each other and running into below error: Erasing and writing flash chip... Timeout error between offset 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED! Uh oh. Erase/write failed. Checking if anything has changed. TEST=Able to flash coreboot image on Alder Lake (Brya variants), Tiger Lake (Volteer variants), Kaby Lake (Eve system), Comet Lake (Hatch variants) and Ivybridge without any failure. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484 Reviewed-on: https://review.coreboot.org/c/flashrom/+/61854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ichspi: Add Alder Lake supportEdward O'Callaghan2022-03-071-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Does exactly what it says on the tin. BUG=b:220799648 TEST=```localhost ~ # flashrom --flash-name <snip> Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. vendor="Programmer" name="Opaque flash chip" flashrom -p internal --ifd -i fd -i bios -r /tmp/filename.rom flashrom unknown on Linux 5.15.22 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). coreboot table found at 0x768a7000. Found chipset "Intel Alder Lake-N". Enabling flash write... Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. SPI Configuration is locked down. OK. Found Winbond flash chip "W25Q256JV_M" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading ich descriptor... done. Using regions: "bios", "fd". Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading flash... done. SUCCESS Also, Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset '600 series Alder Point'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00500000 - 01ffffff named bios Added layout entry 00001000 - 004fffff named me ``` Tested on Nivviks/ADL-N and Brya/ADL-P. Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sam McNally <sammc@google.com>
* Add Elkhart Lake supportWerner Zeh2022-02-041-2/+11
| | | | | | | | | | | | | | | | Elkhart Lake has a chipset called Mule Creek Canyon which is quite compatible with 300 series chipsets. There are a few differences though, e.g. different encoding for the SPI clock values for read and write in the FLCOMP register. In addition Elkhart Lake has a new PCI device ID for the SPI controller which is added, too. TEST=Read and flash complete flash on Siemens MC EHL1 Change-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/60711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Remove unneeded line breaks, add useful line breaks and tabsAnastasia Klimchuk2022-02-021-58/+36
| | | | | | | | | | | | | | | | BUG=b:204488958 TEST=Check that the following scenarios still behave properly: 1) probe-read-verify-erase section-write-reboot on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E 2) flashrom binary built before and after this patch with command `make clean && make CONFIG_EVERYTHING=yes VERSION=none` is the same Change-Id: I7ca2902b7caaa95418b828b068c661afafdcd171 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/60272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Extract initialisation of swseq and hwseq into a functionAnastasia Klimchuk2022-02-021-34/+41
| | | | | | | | | | | | | | | | | | | | | | | | Initialisation of swseq_data and hwseq_data gets its own function, which is called from init_ich_default. This makes init_ich_default more readable. This patch also gives a name to (previously anonymous) struct swseq_data. Its sibling struct hwseq_data already has a name. Structs need names to be able to declare function parameters. BUG=b:204488958 TEST=Check that the following scenarios still behave properly: 1) probe-read-verify-erase section-write-reboot on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E 2) probe and read on Panther Point (7 series PCH) Change-Id: I7d62b1b380e497b82dcae1284d752204cc541bd3 Tested-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Extract handling programmer param into a functionAnastasia Klimchuk2022-02-021-27/+37
| | | | | | | | | | | | | | | | | | | | | Extract processing of ich_spi_mode into a separate function which is called from init_ich_default. This makes init_ich_default more readable and avoids one local variable. BUG=b:204488958 TEST=Check that the following scenarios still behave properly: 1) probe-read-verify-erase section-write-reboot on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E 2) probe and read on Panther Point (7 series PCH) Change-Id: I20e2379a6fd58c9346f0a2d6daf2b8decf1f6976 Tested-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Split very long init function into twoAnastasia Klimchuk2022-02-021-242/+255
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ich_init_spi is very long, but logically it can be split. Init function detects the chipset and then the rest of operations depends on the chipset. Init function is more readable now, it consists of only a switch. Initialisation of hwseq and swseq that used to happen in the beginning of init function now moved to init_ich_default, because hwseq and swseq are only used for chipsets served by init_ich_default. BUG=b:204488958 TEST=Check that the following scenarios still behave properly: 1) probe-read-verify-erase section-write-reboot on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E 2) probe and read on Panther Point (7 series PCH) 3) on machine with ich7 chipset, output from probe and read is the same between master and this patch Change-Id: I6789bc456a4878e6555831ae0b80ecbdbf62938b Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: Nico Huber <nico.h@gmx.de> Tested-by: Nicholas Chin <nic.c3.14@gmail.com> Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58735 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* hwaccess: move mmio functions into hwaccess_physmapThomas Heijligen2022-01-201-1/+0
| | | | | | | | | | | The mmio_le/be_read/writex functions are used for raw memory access. Bundle them with the physmap functions. Change-Id: I313062b078e89630c703038866ac93c651f0f49a Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/61160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* physmap: rename to hwaccess_physmap, create own headerThomas Heijligen2021-12-221-0/+1
| | | | | | | | | | Line up physmap with the other hwaccess related code. Change-Id: Ieba6f4e94cfc3e668fcb8b3c978de5908aed2592 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/60113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add Tiger Lake U Premium supportMichał Żygowski2021-11-171-1/+10
| | | | | | | | | | | | | | | | | | | | | | Tiger Lake has very low ICCRIBA (TGL=0x11, CNL=0x34 and CML=0x34) and detects as unknown chipset compatible with 300 series chipset. Add a new enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to CHIPSET_400_SERIES_COMET_POINT. There are some exceptions though, ICCRIBA is no longer present n descriptor content so a new union has been defined for new fields and used in descriptor guessing. freq_read field is not present on Tiger Lake, moreover in CannonPoint and Comet Point this field is used as eSPI/EC frequency, so a new function to print read frequency has ben added. Finally Tiger lake boot straps include eSPI, so a new bus has been added for the new straps. TEST=Flash BIOS region on Intel i5-1135G7 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* remove compile guardsThomas Heijligen2021-09-261-4/+0
| | | | | | | | | | | | | The build system handles the decision when to build a file. Extra compile guards for the source files are not necessary. Change-Id: I76a76e05c7a7dd27637325ab1e9d8946fd5f9076 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/57797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* treewide: Drop unnecessary uses of memset/memcpyAngel Pons2021-06-091-3/+1
| | | | | | | | | | Simply provide an initialiser or use a direct assignment instead. Change-Id: I07385375cd8eec8a95874001b402b2c17ec09e09 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* treewide: Drop most cases of `sizeof(struct ...)`Angel Pons2021-06-091-1/+1
| | | | | | | | | | | | | | | | Spelling out the struct type name hurts readability and introduces opportunities for bugs to happen when the pointer variable type is changed but the corresponding sizeof is (are) not. TEST=`make CONFIG_EVERYTHING=yes CONFIG_JLINK_SPI=no VERSION=none -j` with and without this patch; the flashrom executable does not change. Change-Id: Icc0b60ca6ef9f5ece6ed2a0e03600bb6ccd7dcc6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* programmer: Smoothen register_opaque_master() APIAnastasia Klimchuk2021-05-231-1/+1
| | | | | | | | | | | | | | | | It was impossible to register a const struct opaque_master that would point to dynamically allocated `data`. Fix that so that we won't have to create more mutable globals. BUG=b:185191942 TEST=builds Change-Id: Id3adb4cf04ae04dbe87ddb96f30871cb5f7c8ff0 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54170 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add Gemini Lake supportAngel Pons2021-05-161-2/+9
| | | | | | | | | | | The SPI hardware is pretty much unchanged from Apollo Lake. However, the IFD differs significantly enough to require special handling. Signed-off-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77 Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* programmer: Smoothen register_spi_master() APINico Huber2021-05-131-3/+3
| | | | | | | | | | | | | It was impossible to register a const struct spi_master that would point to dynamically allocated `data`. Fix that so that we won't have to create more mutable globals. Change-Id: I0c753b3db050fb87d4bbe2301a7ead854f28456f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tree: Remove forward-declarations for spi mastersAnastasia Klimchuk2021-02-161-165/+159
| | | | | | | | | | | | | | | | | Reorder functions to avoid forward-declarations. It looks like for most of the spi masters this has already been done before, I covered remaining small ones in one patch. BUG=b:140394053 TEST=builds Change-Id: I23ff6b79d794876f73b327f18784ca7c04c32c84 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/50711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Add support for Comet Lake-U/400-series PCHMatt DeVillier2020-09-241-1/+10
| | | | | | | | | | | | | | | | Add enum CHIPSET_400_SERIES_COMET_POINT and treat it identically to CHIPSET_300_SERIES_CANNON_POINT. Add PCI IDs for Comet Lake, CML-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT. Test: read/write unlocked CML-U board Change-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* ichspi.c: Make ich_init_spi() parameteric on spibarEdward O'Callaghan2020-07-161-27/+27
| | | | | | | | | | | | The ich_init_spi() function takes spibar as a parameter and sets the global ich_spibar with it but then uses the global symbol instead of using the parameter directly. Change-Id: Id809c33d8a4074acbee8e1cd8e3b7b00ce0cb3ec Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi.c: Make pprinters parametric on ich_generationEdward O'Callaghan2020-07-161-16/+17
| | | | | | | | | | | | | | | Make the two prettyprint functions pure by taking the ich_generation value as a function parameter over a global variable: * prettyprint_ich9_reg_hsfs() * prettyprint_ich9_reg_hsfc() Change-Id: I5d4fb012c6b9b843ac30c1fe2ea6fe754c545a43 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43501 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi.c: Make ich_set_bbar() parameteric on ich_generationEdward O'Callaghan2020-07-161-5/+5
| | | | | | | | | | | Work towards dropping ich_generation global usage and make the ich_set_bbar() function pure. Change-Id: I6da6dccb413cbafa2fbaca213574f22c7a258139 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi.c: Make ich_init_opcodes() parameteric on ich_generationEdward O'Callaghan2020-07-161-13/+13
| | | | | | | | | | | Work towards dropping ich_generation global usage and make the ich_init_opcodes() function pure. Change-Id: I68cc078cc8bc1c772f52ca3e5e12559991180210 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi.c: Make ich_init_spi() parametric on ich_generationEdward O'Callaghan2020-07-161-5/+5
| | | | | | | | | | | Work towards dropping ich_generation global usage and make the ich_init_spi() function more pure. Change-Id: I5293e7ae6f20a2299577172655c2926861091f5a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* const'ify flashctx to align signatures with cros flashromEdward O'Callaghan2020-04-301-2/+2
| | | | | | | | | | | | | | | | The ChromiumOS flashrom fork has since const'ify flashctx in a few places. This aligns the function signatures to match with downstream to ease forward porting patches out of downstream back into mainline flashrom. This patch is minimum viable alignment and so feedback is welcome. Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Replace default JEDEC_BE_D8 with JEDEC_SEDavid Hendricks2019-09-241-1/+1
| | | | | | | | | | | | | | This aligns the upstream master branch with chromium's. On-the-fly opcode reprogramming is supported by both branches so the default opcode shouldn't matter. Review URL: http://codereview.chromium.org/3239001 Change-Id: I379549e8fa966e75e3d8b7932700df62cf50df64 Signed-off-by: Mayur Panchal <panchalm@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Add support for discrete Cannon Lake PCHsNico Huber2019-08-081-11/+33
| | | | | | | | | | | | | | | | Only minor differences in the Firmware Descriptor, compared to their predecessors. We extend our check on the `ICCRIBA` field in the descriptor to dis- tinguish it from older generation. Alas, the `freq_read` field was repurposed, so we can't use it as sanity check any more. Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* Fix -Wsign-compare troubleNico Huber2019-07-311-9/+9
| | | | | | | | | | | Mostly by changing to `unsigned` types where applicable, sometimes `signed` types, and casting as a last resort. Change-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
* ichspi: Add Apollo Lake supportNico Huber2019-07-061-38/+74
| | | | | | | | | | | | | | | It's almost identical to 100 series PCHs and later. There are some additional FREGs (12..15). To not clutter the `if` conditions further, make more use of `switch` statements. Tested on Kontron mAL10. Mark it as DEP as usually the last sector is not covered by the descriptor layout and can't be read. Change-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* spi: Drop spi_controller typeNico Huber2019-06-271-3/+0
| | | | | | | | | | Not needed anymore. Drop it fast before it encourages anyone to violate layers again! Change-Id: I8eda93b429e3ebaef79e22aba76be62987e496f4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33651 Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi.c: Remove unneeded 'else'Elyes HAOUAS2019-06-211-12/+12
| | | | | | | | | | 'else' is not needed after a 'break' or 'return'. Change-Id: Ie000732158f27632ee92404c66a9aab43f3b374c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Rework internal bus handling and laptop bail-outNico Huber2019-06-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | We used to bail out on any unknown laptop. However, modern systems with SPI flashes don't suffer from the original problem. Even if a flash chip is shared with the EC, the latter has to expect the host to send regular JEDEC SPI commands any time. So instead of bailing out, we limit the set of buses to probe. If we suspect to be running on a laptop, we only allow probing of SPI and opaque programmers. The user can still use the existing force options to probe all buses. This will obsolete some board-enables that could be moved to `print.c` in follow-up commits. Change-Id: I1dbda8cf0c10d7786106f14f0d18c3dcce35f0a3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/28716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* Fix several -Wno-implicit-fallthrough warningsRichard Hughes2019-02-111-2/+2
| | | | | | | | | | | | GCC is picky about the comment being where the break should go. Change-Id: I05db2fb34025fefe2c6ddd1274c8e45b7cc5a4b6 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Fix one more -Wmissing-field-initializers warningRichard Hughes2019-02-031-1/+3
| | | | | | | | | | | | | Fixes: ichspi.c: In function ‘ich_init_spi’: ichspi.c:1707:9: warning: missing initializer for field ‘component’ Change-Id: Iee5728167963fece24822ad2e3ab7bd9d444b42c Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/31224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix several -Wno-missing-field-initializers warningsRichard Hughes2019-02-031-1/+1
| | | | | | | | Change-Id: Ib4487d4c1a38fa8471fa1f9034604412e9d14cf7 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix several -Wold-style-declaration warningsRichard Hughes2019-02-031-1/+1
| | | | | | | | Change-Id: Iffe5e652779a13ee7f64696fb5df4a781fe9a632 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Enable writes with active MENico Huber2018-05-291-46/+38
| | | | | | | | | | | | | Replace the `ich_spi_force` logic with more helpful warnings. These can be hidden later, in case the necessary switches are detected. Also, demote some warnings about settings that are the default nowadays (e.g. SPI configuration lock, inaccessible ME region). Change-Id: I94a5e7074b845c227e43d76d04dd1a71082a1cef Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Remove address from GPLv2 headersElyes HAOUAS2018-04-241-4/+0
| | | | | | | | Change-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix whitespace errorsElyes HAOUAS2018-04-241-2/+2
| | | | | | | | Change-Id: Ic2d3bb9d8581a0471a8568a130f893b34dddf113 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* spi: Move ICH BBAR quirk out of the wayNico Huber2017-12-281-14/+25
| | | | | | | | | | | | | | | | | | | | | Get rid of the layering violations around ICH's BBAR. Move all the weird address handling into (surprise, surprise) `ichspi.c`. Might fix writes for the `BBAR != 0` case by accident. Background: Some ICHs have a BBAR (BIOS Base Address Configuration Register) that, if set, limits the valid address range to [BBAR, 2^24). Current code lifted addresses for REMS, RES and READ operations by BBAR, now we do it for all addresses in ichspi. Special care has to be taken if the BBAR is not aligned by the flash chip's size. In this case, the lower part of the chip (from BBAR aligned down, up to BBAR) is inacces- sible (this seems to be the original intend behind BBAR) and has to be left out in the address offset calculation. Change-Id: Icbac513c5339e8aff624870252133284ef85ab73 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22396 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Fix 100 series PCH (Skylake) supportNico Huber2017-12-191-1/+1
| | | | | | | | | | | | | | Pretty subtle missing `else` made flashrom treat Skylake like older chipsets. Change-Id: I14bf578964124d4677cb5dfca01c9d1b0d279c9c Signed-off-by: Nico Huber <nico.h@gmx.de> Reported-by: Youness Alaoui <kakaroto@kakaroto.homelinux.net> Reviewed-on: https://review.coreboot.org/22832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 11:45:26 +0000