diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2020-08-12 12:48:06 -0500 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-09-24 10:47:28 +0000 |
| commit | b1f858f65b2abd276542650d8cb9e382da258967 (patch) | |
| tree | 5e096de6d9ebee4085bb7107fd859873bfe2584b /ichspi.c | |
| parent | cb9f3cd0a70df166ada25bad7f18cc8ea80bac49 (diff) | |
| download | flashrom-b1f858f65b2abd276542650d8cb9e382da258967.tar.gz flashrom-b1f858f65b2abd276542650d8cb9e382da258967.tar.bz2 flashrom-b1f858f65b2abd276542650d8cb9e382da258967.zip | |
Add support for Comet Lake-U/400-series PCH
Add enum CHIPSET_400_SERIES_COMET_POINT and treat it identically
to CHIPSET_300_SERIES_CANNON_POINT.
Add PCI IDs for Comet Lake, CML-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT.
Test: read/write unlocked CML-U board
Change-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/44420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'ichspi.c')
| -rw-r--r-- | ichspi.c | 11 |
1 files changed, 10 insertions, 1 deletions
@@ -399,6 +399,7 @@ static void prettyprint_ich9_reg_hsfs(uint16_t reg_val, enum ich_chipset ich_gen case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: break; default: pprint_reg(HSFS, BERASE, reg_val, ", "); @@ -409,6 +410,7 @@ static void prettyprint_ich9_reg_hsfs(uint16_t reg_val, enum ich_chipset ich_gen case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", "); pprint_reg(HSFS, WRSDIS, reg_val, ", "); break; @@ -428,6 +430,7 @@ static void prettyprint_ich9_reg_hsfc(uint16_t reg_val, enum ich_chipset ich_gen case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", "); pprint_reg(HSFC, WET, reg_val, ", "); break; @@ -1741,6 +1744,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen) case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: num_pr = 6; /* Includes GPR0 */ reg_pr0 = PCH100_REG_FPR0; @@ -1772,6 +1776,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen) num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ break; case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: num_freg = 16; break; @@ -1867,6 +1872,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen) case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: tmp = mmio_readl(spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); @@ -1941,6 +1947,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen) case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_BAYTRAIL: break; @@ -1973,6 +1980,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen) case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: break; default: @@ -2004,7 +2012,8 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen) if (ich_spi_mode == ich_auto && (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || - ich_gen == CHIPSET_300_SERIES_CANNON_POINT)) { + ich_gen == CHIPSET_300_SERIES_CANNON_POINT || + ich_gen == CHIPSET_400_SERIES_COMET_POINT)) { msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n"); ich_spi_mode = ich_hwseq; } |