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authorNico Huber <nico.h@gmx.de>2021-05-11 17:38:14 +0200
committerNico Huber <nico.h@gmx.de>2021-05-13 14:37:29 +0000
commit7e4968525d37d87e8b6f8b848e4f2f9696926237 (patch)
treecefab4e871fc4e32e15772e131942c8fa5712a13 /ichspi.c
parentc1173784781d81c5d601a65fbfc61d550d50f377 (diff)
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programmer: Smoothen register_spi_master() API
It was impossible to register a const struct spi_master that would point to dynamically allocated `data`. Fix that so that we won't have to create more mutable globals. Change-Id: I0c753b3db050fb87d4bbe2301a7ead854f28456f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'ichspi.c')
-rw-r--r--ichspi.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/ichspi.c b/ichspi.c
index e45b39a6..613f3fc3 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1812,7 +1812,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
}
ich_init_opcodes(ich_gen);
ich_set_bbar(0, ich_gen);
- register_spi_master(&spi_master_ich7);
+ register_spi_master(&spi_master_ich7, NULL);
break;
case CHIPSET_ICH8:
default: /* Future version might behave the same */
@@ -2041,7 +2041,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
register_opaque_master(&opaque_master_ich_hwseq);
} else {
- register_spi_master(&spi_master_ich9);
+ register_spi_master(&spi_master_ich9, NULL);
}
break;
}
@@ -2071,7 +2071,7 @@ int via_init_spi(uint32_t mmio_base)
/* Not sure if it speaks all these bus protocols. */
internal_buses_supported &= BUS_LPC | BUS_FWH;
ich_generation = CHIPSET_ICH7;
- register_spi_master(&spi_master_via);
+ register_spi_master(&spi_master_via, NULL);
msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));